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1. WO2020134965 - MANUFACTURING METHOD AND DEVICE FOR ARRAY SUBSTRATE, AND ARRAY SUBSTRATE

Publication Number WO/2020/134965
Publication Date 02.07.2020
International Application No. PCT/CN2019/123618
International Filing Date 06.12.2019
IPC
H01L 29/06 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02Semiconductor bodies
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
CPC
H01L 21/84
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
84the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 27/12
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/06
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
H01L 29/786
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
76Unipolar devices ; , e.g. field effect transistors
772Field effect transistors
78with field effect produced by an insulated gate
786Thin film transistors, ; i.e. transistors with a channel being at least partly a thin film
Applicants
  • 惠科股份有限公司 HKC CORPORATION LIMITED [CN]/[CN]
Inventors
  • 莫琼花 MO, Qionghua
  • 卓恩宗 CHO, En-tsung
Agents
  • 深圳市世纪恒程知识产权代理事务所 CENFO INTELLECTUAL PROPERTY AGENCY
Priority Data
201811598405.425.12.2018CN
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) MANUFACTURING METHOD AND DEVICE FOR ARRAY SUBSTRATE, AND ARRAY SUBSTRATE
(FR) PROCÉDÉ ET DISPOSITIF DE FABRICATION DE SUBSTRAT MATRICIEL, ET SUBSTRAT MATRICIEL
(ZH) 阵列基板的制造方法、装置及阵列基板
Abstract
(EN)
An array substrate and a manufacturing method and device therefor. Said method comprises: forming, by means of deposition, a gate insulation layer (30) on a base substrate (10) and a gate electrode (20) which are formed in advance, the gate insulation layer (30) covering the gate electrode (20); sequentially forming, by means of deposition, on the gate insulation layer (30) an amorphous silicon layer (40), a doped amorphous silicon layer (50) comprising at least three doped layers, and a metal layer (60), the doping concentrations of various layers of the doped amorphous silicon layer (50) increasing layer by layer from bottom to top; and forming, by etching, patterns of the amorphous silicon layer (40), the doped amorphous silicon layer (50) and the metal layer (60), so as to form an array substrate.
(FR)
La présente invention concerne un substrat matriciel et son procédé et son dispositif de fabrication. Ledit procédé consiste : à former, au moyen d'un dépôt, une couche d'isolation de grille (30) sur un substrat de base (10) et une électrode de grille (20) qui sont formées à l'avance, la couche d'isolation de grille (30) recouvrant l'électrode de grille (20) ; à former séquentiellement, au moyen d'un dépôt, sur la couche d'isolation de grille (30), une couche de silicium amorphe (40), une couche de silicium amorphe dopée (50) comprenant au moins trois couches dopées, et une couche métallique (60), les concentrations de dopage de diverses couches de la couche de silicium amorphe dopée (50) augmentant couche par couche de bas en haut ; et à former, par gravure, des motifs de la couche de silicium amorphe (40), de la couche de silicium amorphe dopée (50) et de la couche métallique (60), de manière à former un substrat matriciel.
(ZH)
一种阵列基板及其制造方法与装置,包括:在预先形成的衬底基板(10)和栅极(20)上沉积形成栅极绝缘层(30),所述栅极绝缘层(30)覆盖所述栅极(20);在所述栅极绝缘层(30)上依次沉积形成非晶硅层(40)、包括至少三层掺杂层的掺杂型非晶硅层(50)和金属层(60),其中,所述掺杂型非晶硅层(50)各层的掺杂浓度自下往上逐层递增;蚀刻出所述非晶硅层(40)、所述掺杂型非晶硅层(50)和所述金属层(60)的图形,形成阵列基板。
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Latest bibliographic data on file with the International Bureau