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1. WO2020134722 - FLIP-CHIP ASSEMBLY, FLIP-CHIP PACKAGING STRUCTURE, AND MANUFACTURING METHOD

Publication Number WO/2020/134722
Publication Date 02.07.2020
International Application No. PCT/CN2019/119478
International Filing Date 19.11.2019
IPC
H01L 23/488 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488consisting of soldered or bonded constructions
H01L 23/31 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulation, e.g. encapsulating layers, coatings
31characterised by the arrangement
H01L 21/56 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56Encapsulations, e.g. encapsulating layers, coatings
CPC
H01L 21/56
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
H01L 23/31
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulations, e.g. encapsulating layers, coatings, ; e.g. for protection
31characterised by the arrangement ; or shape
H01L 23/488
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; ; Selection of materials therefor
488consisting of soldered ; or bonded; constructions
Applicants
  • 颀中科技(苏州)有限公司 CHIPMORE TECHNOLOGY CORPORATION LIMITED [CN]/[CN]
Inventors
  • 梅嬿 MEI, Yan
Agents
  • 苏州威世朋知识产权代理事务所(普通合伙) SUZHOU WISPRO INTELLECTUAL PROPERTY AGENCY
Priority Data
201811638810.429.12.2018CN
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) FLIP-CHIP ASSEMBLY, FLIP-CHIP PACKAGING STRUCTURE, AND MANUFACTURING METHOD
(FR) ENSEMBLE PUCE RETOURNÉE, STRUCTURE D'ENCAPSULATION DE PUCE RETOURNÉE ET SON PROCÉDÉ DE FABRICATION
(ZH) 倒装芯片组件、倒装芯片封装结构及制备方法
Abstract
(EN)
Provided are a flip-chip assembly, a flip-chip packaging structure, and a manufacturing method. The flip-chip assembly comprises a chip, and a first conductive post and a second conductive post formed at a side surface of the chip along a first direction, wherein the second conductive post is larger than the first conductive post, a first solder bump is provided at one end of the first conductive post away from the chip, multiple mutually spaced-apart second solder bumps are provided at one end of the second conductive post away from the chip, and conductive bases are further provided between the second solder bumps and the second conductive post. The manufacturing method for the flip-chip assembly comprises: fabricating the multiple mutually spaced-apart conductive bases on the second conductive post, fabricating the corresponding second solder bumps on the conductive bases, and converting the first solder bump and the second solder bumps from an initial state to a finished state by means of a thermal treatment. The present invention adjusts solder structures on the second conductive post having a strip or elliptical shape and a large size, thereby improving product quality.
(FR)
L'invention concerne un ensemble puce retournée, une structure d'encapsulation de puce retournée et son procédé de fabrication. L'ensemble puce retournée comprend une puce, et un premier montant conducteur et un second montant conducteur formés au niveau d'une surface latérale de la puce le long d'une première direction, le second montant conducteur étant plus grand que le premier montant conducteur, une première perle de soudure est disposée au niveau d'une extrémité du premier montant conducteur à l'opposé de la puce, de multiples secondes perles de soudure espacées les unes des autres sont disposées au niveau d'une extrémité du second montant conducteur à l'opposé de la puce, et des bases conductrices sont en outre disposées entre les secondes perles de soudure et le second montant conducteur. Le procédé de fabrication de l'ensemble puce retournée consiste à : fabriquer les multiples bases conductrices mutuellement espacées sur le second montant conducteur, fabriquer les secondes perles de soudure correspondantes sur les bases conductrices, et convertir la première perle de soudure et les secondes perles de soudure d'un état initial à un état fini au moyen d'un traitement thermique. La présente invention ajuste des structures de soudure sur le second montant conducteur ayant une forme de bande ou elliptique et une grande taille, ce qui permet d'améliorer la qualité du produit.
(ZH)
本发明提供了一种倒装芯片组件、倒装芯片封装结构及制备方法,所述倒装芯片组件包括芯片、沿第一方向形成在所述芯片一侧表面的第一导电柱与第二导电柱,所述第二导电柱大于第一导电柱,所述第一导电柱背离所述芯片的一端设有第一焊料块;所述第二导电柱背离所述芯片的一端设置有若干相互间隔的第二焊料块,且所述第二焊料块与第二导电柱之间还设有的导电底座。所述倒装芯片组件的制备方法包括在第二导电柱上制得若干相互间隔的导电底座,再于导电底座上制得相应的第二焊料块,再通过热处理使得第一焊料块及第二焊料块由初始状态转换至成品状态。本发明针对条状、椭圆状等具有较大尺寸的第二导电柱上的焊料结构进行调整,提高产品质量。
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