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1. WO2020133804 - ARRAY SUBSTRATE AND METHOD FOR PREPARING SAME

Publication Number WO/2020/133804
Publication Date 02.07.2020
International Application No. PCT/CN2019/082654
International Filing Date 15.04.2019
IPC
G02F 1/13 2006.1
GPHYSICS
02OPTICS
FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01for the control of the intensity, phase, polarisation or colour
13based on liquid crystals, e.g. single liquid crystal display cells
CPC
G02F 1/13
GPHYSICS
02OPTICS
FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01for the control of the intensity, phase, polarisation or colour 
13based on liquid crystals, e.g. single liquid crystal display cells
H01L 21/84
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
84the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 27/12
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12the substrate being other than a semiconductor body, e.g. an insulating body
Applicants
  • 武汉华星光电技术有限公司 WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN]/[CN]
Inventors
  • 卢改平 LU, Gaiping
  • 唐维 TANG, Wei
  • 黄建龙 HUANG, Jianlong
Agents
  • 深圳翼盛智成知识产权事务所(普通合伙) ESSEN PATENT & TRADEMARK AGENCY
Priority Data
201811615770.127.12.2018CN
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) ARRAY SUBSTRATE AND METHOD FOR PREPARING SAME
(FR) SUBSTRAT MATRICIEL ET SON PROCÉDÉ DE PRÉPARATION
(ZH) 阵列基板及其制备方法
Abstract
(EN)
An array substrate and a method for preparing same, the array substrate comprising a base layer (1), a first thin film transistor structure layer (2), a flat layer (3), a flat layer groove (32), and a second thin film transistor structure layer (4). The method for preparing the array substrate comprises: a base layer provision step (S1), a first thin film transistor structure layer preparation step (S2), a flat layer preparation step (S3), a flat layer groove-opening step (S4), and a second thin film transistor structure layer preparation step (S5). The technical effects of the present invention lie in protecting dense metal traces, preventing poor PI coating accuracy, and so on.
(FR)
Substrat matriciel et son procédé de préparation, le substrat de réseau comprenant une couche de base (1), une première couche de structure de transistor à film mince (2), une couche plate (3), une rainure de couche plate (32), et une seconde couche de structure de transistor à film mince (4). Le procédé de préparation du substrat matriciel comprend les étapes suivantes: fourniture de couche de base (S1), une première préparation de couche de structure de transistor à film mince (S2), préparation de couche plate (S3), ouverture de rainure de couche plate (S4), et une seconde préparation de couche de structure de transistor à film mince (S5). Les effets techniques de la présente invention résident dans la protection contre les traces métalliques denses, le fait d'empêcher une mauvaise précision du revêtement en PI, etc.
(ZH)
一种阵列基板及其制备方法,所述阵列基板包括:基层(1)、第一薄膜晶体管结构层(2)、平坦层(3)、平坦层凹槽(32)以及第二薄膜晶体管结构层(4)。所述阵列基板的制备方法包括:基层设置步骤(S1)、第一薄膜晶体管结构层制备步骤(S2)、平坦层制备步骤(S3)、平坦层开槽步骤(S4)以及第二薄膜晶体管结构层制备步骤(S5)。本发明的技术效果在于,保护密集的金属走线,防止PI涂布精度差等情况。
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