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1. WO2020132909 - CHIP PACKAGING STRUCTURE

Publication Number WO/2020/132909
Publication Date 02.07.2020
International Application No. PCT/CN2018/123686
International Filing Date 26.12.2018
IPC
H01L 23/538 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
538the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
CPC
H01L 23/538
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
538the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
Applicants
  • 华为技术有限公司 HUAWEI TECHNOLOGIES CO., LTD. [CN]/[CN]
Inventors
  • 符会利 FU, HuiLi
  • 郭茂 GUO, Mao
  • 张晓东 ZHANG, Xiaodong
Priority Data
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) CHIP PACKAGING STRUCTURE
(FR) STRUCTURE DE MISE SOUS BOÎTIER DE PUCES
(ZH) 一种芯片的封装结构
Abstract
(EN)
A packaging structure comprises a wiring board (22) and two chips (10, 20) respectively attached to upper and lower surfaces of the wiring board (22). The upper and lower two chips (10, 20) are directly attached to the wiring board (22), thereby reducing the thickness of the chip packaging structure.
(FR)
Une structure de mise sous boîtier comprend une carte de câblage (22) et deux puces (10, 20) fixées respectivement à des surfaces supérieure et inférieure de la carte de câblage (22). Les deux puces supérieure et inférieure (10, 20) sont directement fixées à la carte de câblage (22), réduisant ainsi l'épaisseur de la structure de mise sous boîtier de puces.
(ZH)
一种封装结构,包括布线板(22),以及贴附于所述布线板(22)上下两面的两个芯片(10、20)。由于上下两个芯片(10、20)直接贴附于所述布线板(22)上,从而减小了芯片封装的厚度。
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