Processing

Please wait...

Settings

Settings

Goto Application

1. WO2020118095 - RF RECEIVER ARCHITECTURES WITH PARAMETRIC CIRCUITS

Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

[ EN ]

CLAIMS

What is claimed is:

1. An RF receiver circuit design limited by conditions and frequencies to

simultaneously provide steady state low-noise signal amplification, frequency down-conversion and image signal rejection, the RF receiver circuit design comprising:

an antenna coupled to an input of a first RF band select filter RF-BPFl with center frequency FIN which is connected on an output side to an input side of a low-noise amplifier LNA;

a second RF band select filter RF-BPF2 with center frequency FIN connected on an input side to the output of low-noise amplifier LNA and connected on an output side to an input side of a mixer block;

a variable gain amplifier VGA coupled on an input side to an output of the mixer block and coupled on an output side to an input of an analog-to-digital converter from whose output is coupled a base-band block BB; and

wherein the mixer block comprises a first parametric diode circuit PARI connected at a first input to filter RF-BPF2 and connected at a second input to a local oscillator LO with frequency F and further connected at an output to an input side of an IF filter IF-BPF with center frequency FIF.

2. The RF receiver circuit design of claim 1, wherein frequency F=FIN+FIF

3. The RF receiver circuit design of claim 2, wherein the frequency pair (FIN, FIF) comprises one of the pairs (1.575GHz, 0.008GHz), (19GHz, 3GHz), (28GHz,

3 GHz), (39GHz, 5GHz), (66GHz, 5GHz), (77GHz,5GHz), or (94GHz, 5GHz).

4. The RF receiver circuit design of claim 3, wherein band select filter RF-BF1 comprises one of a BAW or SAW filter and is connected on its output side to the input side of the mixer block eliminating low-noise amplifier LNA and second band select filter RF-BPF2, and wherein parametric diode circuit PARI operates as a low-noise amplifier with down-conversion and image rejection.

5. The RF receiver circuit design of claim 3, implemented as one of a CMOS single chip device or as part of an integrated system of CMOS components.

6. An RF receiver circuit design limited by conditions and frequencies to

simultaneously provide steady state low-noise signal amplification, frequency down-conversion and image signal rejection, the RF receiver circuit design comprising:

an antenna coupled to an input of a first RF band select filter RF-BPFl with center frequency FIN which is connected on an output side to an input side of a mixer block;

a variable gain amplifier VGA coupled on an input side to an output of the mixer block and coupled on an output side to an input of an analog-to-digital converter from whose output is coupled a base-band block BB;

wherein the mixer block comprises:

a first parametric diode circuit PARI connected at a first input to filter RF- BPFl and connected at a second input to a local oscillator LO with frequency F and further connected at an output to an input side of a second RF band select filter RF-BPF2 with center frequency F-FIN; and

a second parametric diode circuit PAR2 connected at a first input to filter RF-BPF2 and coupled at a second input through a divide by two frequency divider to local oscillator LO and further connected at an output to an input side of an IF filter IF-BPF with center frequency FIF.

7. The RF receiver circuit design of claim 6, wherein frequency F=2FIN-2FIF.

8. The RF receiver circuit design of claim 7 wherein the frequency pair (FIN, FIF) comprises one of the pairs (1.575GHz, 0.008GHz), (19GHz, 3GHz), (28GHz,

3 GHz), (39GHz, 5GHz), (66GHz, 5GHz), (77GHz,5GHz), or (94GHz, 5GHz).

9. The RF receiver circuit design of claim 8, wherein:

the first RF band select filter RF-BPFl is connected on an output side to an input side of a low-noise amplifier LNA and the output of low-noise amplifier LNA and connected on an output side to an input side of the mixer block; and

wherein parametric diode circuits PARI and PAR2 operate as a low-noise amplifier with down-conversion and image rejection.

10. The RF receiver circuit design of claim 8 implemented as one of a CMOS single chip device or as part of an integrated system of CMOS components.

11. An RF receiver circuit design limited by conditions and frequencies to

simultaneously provide steady state low-noise signal amplification, frequency down-conversion and image signal rejection, the RF receiver circuit design comprising:

an antenna coupled to an input of a first RF band select filter RF-BPFl with center frequency FIN which is connected on an output side to an input side of a mixer block;

a variable gain amplifier VGA coupled on an input side to an output of the mixer block and coupled on an output side to an input of an analog-to-digital converter from whose output is coupled a base-band block BB;

wherein the mixer block comprises:

a first parametric diode circuit PART connected at a first input to filter RF- BPFl and connected at a second input through a divide by two frequency divider to a local oscillator LO with frequency F and further connected at an output to an input side of a second RF band select filter RF-BPF2 with center frequency F-FIN; and

a second parametric diode circuit PAR2 connected at a first input to filter RF-BPF2 and coupled at a second input to local oscillator LO with frequency F and further connected at an output to an input side of an IF filter IF-BPF with center frequency FIF.

12. The RF receiver circuit design of claim 11, wherein frequency F=2FIN+2FIF.

13. The RF receiver circuit design of claim 12, wherein the frequency pair (FIN, FIF) comprises one of the pairs (1.575GHz, 0.008GHz), (19GHz, 3GHz), (28GHz,

3 GHz), (39GHz, 5GHz), (66GHz, 5GHz), (77GHz,5GHz), or (94GHz, 5GHz).

14. The RF receiver circuit design of claim 13, wherein:

the first RF band select filter RF-BPFl is connected on an output side to an input side of a low-noise amplifier LNA and the output of low-noise amplifier LNA and connected on an output side to an input side of the mixer block; and

wherein parametric diode circuits PART and PAR.2 operate as a low-noise amplifier with up-conversion and down-conversion and image rejection with low noise figure for the overall receiver chain.

15. The RF receiver circuit design of claim 13, implemented as one of a CMOS single chip device or as part of an integrated system of CMOS components.

16. An RF receiver circuit design limited by conditions and frequencies to simultaneously provide steady state low-noise signal amplification, frequency down-conversion and image signal rejection, the RF receiver circuit design comprising:

an input resonant circuit with resonant frequency 0J' and resonant resistance

R1 and an output resonant circuit with frequency 0J- and resonant resistance R2, wherein the input and output resonant circuits are connected in parallel and are additionally connected together in series via a varactor diode;

a local oscillator with frequency
and pump signal source voltage Vpump = pump cos(iv ,;;m/,/j applied in series with the varactor diode represented as a variable non-linear capacitance C(V) with simplified charge model with second

order non-linear characteristic: ^ c
+ a^c ยท

a limiting design condition whereby local oscillator with frequency
comprises one of copump = wi + w2 or copump = w - w ;

a limiting design condition for a conversion gain greater than 1 at output


a limiting design condition for a stable down-conversion from input frequency co' to output frequency (0- wherein:


17. The RF receiver circuit design of claim 16, wherein a pump parameter defined as PumpX = 2ja2 oico2Ri R2A l p^2ump and indicates the critical pump voltage amplitude

A p.ump at which the circuit starts oscillating, exceeds 0.4.

18. The RF receiver circuit design of claim 17, comprising:

local oscillator with frequency pump = 1571 MHz;

input resonant circuit resonant frequency 0J' = 1575 MHz; and

output resonant circuit frequency wi = 4 MHz.

19. The RF receiver circuit design of claim 17, implemented as one of a CMOS single chip device or as part of an integrated system of CMOS components.