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1. WO2020117893 - ANALOG TO DIGITAL CONVERTER MODULE AND METHOD THEREOF

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[ EN ]

CLAIMS

1 . A method, comprising:

tuning a first signal to create a tuned first signal operating in a first frequency band;

transmitting the tuned first signal along a first cable associated with a first channel;

splitting the tuned first signal into first portion and a second portion;

transmitting the first portion of the tuned first signal along a first segment of the first cable towards a first low frequency Analog to Digital Converter (ADC);

transmitting the second portion of the tuned first signal along a second segment of the first cable towards a first high frequency ADC;

sampling, with a first clock coupled to the first low frequency ADC, the tuned first signal at a first sample rate;

sampling, with a second clock coupled to the first high frequency ADC, the tuned first signal at a second sample rate, wherein the first sample rate is faster than the second sample rate;

converting, in the first low frequency ADC, the tuned first signal from analog form into a digital form; and

converting, in the first high frequency ADC, the tuned first signal from analog form into a digital form.

2. The method of Claim 1 , further comprising:

transmitting the tuned first signal in digital form to a first channel input in a first field programmable gate array (FPGA); and

transmitting the tuned first signal in digital form to a first channel input in a second FPGA.

3. The method of Claim 1 , further comprising:

filtering, via a first bandpass filter, the tuned first signal prior to splitting the tuned first signal in the first splitter;

filtering, via a first low pass filter, the first portion of the tuned first signal along the first segment of the first cable upstream from the first low frequency ADC; and

filtering, via a first high pass filter, the second portion of the tuned first signal along the second segment of the first cable upstream from the first high frequency ADC.

4. The method of Claim 2, further comprising:

tuning a second signal to create a tuned second signal operating in a second frequency band;

transmitting the tuned second signal along a second cable associated with a second channel;

splitting the tuned second signal into first portion and a second portion, wherein each portion of the tuned second signal includes the second frequency band;

transmitting the first portion of the tuned second signal along a first segment of the second cable towards a second low frequency ADC;

transmitting the second portion of the tuned second signal along a second segment of the second cable towards a second high frequency ADC;

sampling, with the first clock coupled to the second low frequency ADC, the tuned second signal at the first sample rate;

sampling, with the second clock coupled to the second high frequency ADC, the tuned second signal at the second sample rate;

converting, in the second low frequency ADC, the tuned second signal from analog form into a digital form;

converting, in the second high frequency ADC, the tuned second signal from analog form into a digital form;

transmitting the tuned second signal in digital form, after sampling in the second low frequency ADC, to a second channel input in the first FPGA; and

transmitting the tuned second signal in digital form, after sampling in the second high frequency ADC, to a second channel input in the second FPGA.

5. The method of Claim 4, further comprising:

filtering, with a second bandpass filter, the tuned second signal prior to splitting the tuned second signal in the second splitter;

filtering, via a second low pass filter, the first portion of the tuned second signal along the first segment of the second cable upstream from the second low frequency ADC; and

filtering, via a second high pass filter, the second portion of the tuned second signal along the second segment of the second cable upstream from the second high frequency ADC.

6. The method of Claim 4, further comprising:

tuning a third signal to create a tuned third signal operating in a third frequency band;

transmitting the tuned third signal along a third cable associated with a third channel;

splitting the tuned third signal into first portion and a second portion, wherein each portion of the tuned third signal includes the third frequency band;

transmitting the first portion of the tuned third signal along a first segment of the third cable towards a third low frequency ADC;

transmitting the second portion of the tuned third signal along a second segment of the third cable towards a third high frequency ADC;

sampling, with the first clock coupled to the third low frequency ADC, the tuned third signal at the first sample rate;

sampling, with the second clock coupled to the third high frequency ADC, the tuned third signal at the second sample rate;

converting, in the third low frequency ADC, the tuned third signal from analog form into a digital form;

converting, in the third high frequency ADC, the tuned third signal from analog form into a digital form;

transmitting the tuned third signal in digital form, after sampling in the third low frequency ADC, to a third channel input in the first FPGA; and

transmitting the tuned third signal in digital form, after sampling in the third high frequency ADC, to a third channel input in the second FPGA.

7. The method of Claim 6, further comprising:

filtering, with a third bandpass filter, the tuned third signal prior to splitting the tuned third signal in the third splitter;

filtering, via a third low pass filter, the first portion of the tuned third signal along the first segment of the third cable upstream from the third low frequency ADC; and

filtering, via a third high pass filter, the second portion of the tuned third signal along the second segment of the third cable upstream from the third high frequency ADC.

8. The method of Claim 6, further comprising:

tuning a fourth signal to create a tuned fourth signal operating in a fourth frequency band;

transmitting the tuned fourth signal along a fourth cable associated with a fourth channel;

splitting the tuned fourth signal into first portion and a second portion, wherein each portion of the tuned fourth signal includes the fourth frequency band;

transmitting the first portion of the tuned fourth signal along a first segment of the fourth cable towards a fourth low frequency ADC;

transmitting the second portion of the tuned fourth signal along a second segment of the fourth cable towards a fourth high frequency ADC;

sampling, with the first clock coupled to the fourth low frequency ADC, the tuned fourth signal after filtering at the first sample rate;

sampling, with the second clock coupled to the fourth high frequency ADC, the tuned fourth signal after filtering at the second sample rate;

converting, in the fourth low frequency ADC, the tuned fourth signal from analog form into a digital form;

converting, in the fourth high frequency ADC, the tuned fourth signal from analog form into a digital form;

transmitting the tuned fourth signal in digital form, after sampling in the fourth low frequency ADC, to a fourth channel input in the first FPGA; and

transmitting the tuned fourth signal in digital form, after sampling in the fourth high frequency ADC, to a fourth channel input in the second FPGA.

9. The method of Claim 8, further comprising:

filtering, with a fourth bandpass filter, the tuned fourth signal prior to splitting the tuned fourth signal in the fourth splitter;

filtering, with a fourth low pass filter, the first portion of the tuned fourth signal along the first segment of the fourth cable upstream from the fourth low frequency ADC; and

filtering, with a fourth high pass filter, the second portion of the tuned fourth signal along the second segment of the fourth cable upstream from the fourth high frequency ADC.

10. The method of Claim 8, further comprising:

wherein the ADC module is a replacement for a legacy ADC module on a platform between a tuner and the first FPGA;

reusing other legacy components on the platform coupled to the ADC module having the first through fourth low frequency ADCs and the first through fourth high frequency ADCs; and

increasing bandwidth throughput along a radio frequency (RF) cable on the platform subsequent to replacing the legacy ADC module.

1 1. The method of Claim 10, wherein a number of ADCs in the first ADC modules doubles a number of channels in the tuner.

12. A platform having legacy radio frequency cables transmitting a first frequency capacity when used with a legacy first analog-to-digital converter (ADC) module that, when replaced with a second ADC module transmits a second frequency capacity greater than the first frequency capacity along the legacy RF cables, the second ADC module comprising:

a first channel;

a first bandpass filter along the first channel;

a first splitter downstream from the first bandpass filter that splits the first channel into a first segment and a second segment;

a first low pass filter along the first segment of the first channel;

a first low frequency ADC coupled to the first segment of the first channel;

a first high pass filter along the second segment of the first channel; and a first high frequency ADC coupled to the second segment of the first channel; wherein the second ADC module increases bandwidth throughput along the legacy RF cable on the platform subsequent to replacing the first ADC module.

13. The platform of Claim 12, wherein the second ADC module comprises:

a second channel;

a second bandpass filter along the second channel;

a second splitter downstream from the second bandpass filter that splits the second channel into a first segment and a second segment;

a second low pass filter along the first segment of the second channel;

a second low frequency ADC coupled to the first segment of the second channel;

a second high pass filter along the second segment of the second channel; and

a second high frequency ADC coupled to the second segment of the second channel.

14. The platform of Claim 13, wherein the second ADC module comprises:

a third channel;

a third bandpass filter along the third channel;

a third splitter downstream from the third bandpass filter that splits the third channel into a first segment and a second segment;

a third low pass filter along the first segment of the third channel;

a third low frequency ADC coupled to the first segment of the third channel; a third high pass filter along the second segment of the third channel; and a third high frequency ADC coupled to the second segment of the third channel.

15. The platform of Claim 14, wherein the second ADC module comprises:

a fourth channel;

a fourth bandpass filter along the fourth channel;

a fourth splitter downstream from the fourth bandpass filter that splits the fourth channel into a first segment and a second segment;

a fourth low pass filter along the first segment of the fourth channel;

a fourth low frequency ADC coupled to the first segment of the fourth channel; a fourth high pass filter along the second segment of the fourth channel; and a fourth high frequency ADC coupled to the second segment of the fourth channel.

16. The platform of Claim 15, wherein the number of ADCs in the second ADC module at least doubles the number of ADCs that were present in the legacy first ADC module.

17. The platform of Claim 15, wherein the number of ADCs in the second ADC module is double a number of channels output from a legacy tuner upstream from the second ADC module.

18. A method comprising:

disconnecting a legacy analog-to-digital (ADC) module a legacy radio frequency (RF) cable on a platform;

disconnecting the legacy ADC module from a circuit downstream from the legacy ADC module;

connecting a first ADC module to the legacy RF cable and the circuit, wherein the first ADC module includes a plurality of ADCs doubling that which were present in the legacy ADC module; and

transmitting an analog signal along the legacy RF cable;

splitting the analog signal, via a splitter in the first ADC module, into two segments, wherein each segment transmits the entire analog signal.

19. The method of Claim 18, further comprising:

filtering, with a first filter, the analog signal in a first segment subsequent to splitting the analog signal; and

filtering, with a different second filter, the analog signal in a second segment subsequent to splitting the analog signal.

20. The method of Claim 18, further comprising:

doubling a number of ADCs in the first ADC module relative to a number of channels in a legacy tuner coupled to the legacy RF cable.