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1. WO2020117678 - NON-POWER OF TWO MEMORY CONFIGURATION

Publication Number WO/2020/117678
Publication Date 11.06.2020
International Application No. PCT/US2019/064017
International Filing Date 02.12.2019
IPC
G06F 12/06 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
06Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
CPC
G06F 12/0607
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
0607Interleaved addressing
G06F 12/0623
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
0615Address space extension
0623for memory modules
G06F 13/16
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
G06F 13/1647
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
1605based on arbitration
1647with interleaved bank access
G06F 13/1657
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
1605based on arbitration
1652in a multiprocessor architecture
1657Access to multiple memories
G06F 13/1684
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
1668Details of memory controller
1684using multiple buses
Applicants
  • ADVANCED MICRO DEVICES, INC. [US]/[US]
Inventors
  • PILLAI, Pazhani
Agents
  • RANKIN, Rory, D.
Priority Data
16/208,13903.12.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) NON-POWER OF TWO MEMORY CONFIGURATION
(FR) CONFIGURATION DE MÉMOIRES N’ÉTANT PAS UNE PUISSANCE DE DEUX
Abstract
(EN)
Systems, apparatuses, and methods for managing a non-power of two memory configuration are disclosed. A computing system includes at least one or more clients, a control unit, and a memory subsystem with a non-power of two number of active memory channels. The control unit reduces a ratio of the number of active memory channels over the total number of physical memory channels to a ratio of a first number to a second number. If a first subset of physical address bits of a received memory request are greater than or equal to the first number, the control unit calculates a third number which is equal to a second subset of physical address bits modulo the first number and the control unit uses a concatenation of the third number and a third subset of physical address bits to select a memory channel for issuing the received memory request.
(FR)
La présente invention concerne des systèmes, des appareils et des procédés de gestion d’une configuration de mémoires n’étant pas une puissance de deux. Un système informatique comprend au moins un ou plusieurs clients, une unité de commande et un sous-système de mémoire avec un nombre de canaux de mémoire actifs qui n'est pas une puissance de deux. L’unité de commande réduit un rapport du nombre de canaux de mémoire actifs sur le nombre total des canaux de mémoire physiques à un rapport d’un premier nombre sur un deuxième nombre. Si un premier sous-ensemble de bits d’adresse physique d’une demande de mémoire reçue est supérieur ou égal au premier nombre, l’unité de commande calcule un troisième nombre qui est supérieur à un deuxième sous-ensemble de bits d’adresse physique modulo le premier nombre et l’unité de commande utilise une concaténation du troisième nombre et d’un troisième sous-ensemble de bits d’adresse physique pour sélectionner un canal de mémoire pour résoudre la demande de mémoire reçue.
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