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1. WO2020117666 - PROTECTION AGAINST TIMING-BASED SECURITY ATTACKS ON RE-ORDER BUFFERS

Publication Number WO/2020/117666
Publication Date 11.06.2020
International Application No. PCT/US2019/063991
International Filing Date 02.12.2019
IPC
G06F 21/55 2013.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
21Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
50Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
55Detecting local intrusion or implementing counter-measures
G06F 21/52 2013.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
21Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
50Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
52during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure
G06F 9/38 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
CPC
G06F 21/71
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
21Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
71to assure secure computing or processing of information
G06F 9/3855
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
3855Reordering, e.g. using a queue, age tags
G06F 9/50
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
50Allocation of resources, e.g. of the central processing unit [CPU]
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • WALLACH, Steven
Agents
  • WARD, John P.
Priority Data
16/210,60905.12.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) PROTECTION AGAINST TIMING-BASED SECURITY ATTACKS ON RE-ORDER BUFFERS
(FR) PROTECTION CONTRE DES ATTAQUES DE SÉCURITÉ BASÉES SUR LA SYNCHRONISATION SUR DES TAMPONS DE RÉORDONNANCEMENT
Abstract
(EN)
Methods, systems, and apparatuses related to re-order buffers and for protection from timing-based security attacks are described. A processor may have functional units configured to execute instructions out of order, a re-order buffer configured to buffer the execution results of instructions for output in order, and a controller configured to randomize data timing in the re-order buffer. For example, the controller can make random adjustments to the capacity of the re-order buffer in buffering and/or sorting execution results and thus randomize data timing in the re-order buffer.
(FR)
L'invention concerne des procédés, des systèmes, et des appareils associés à des tampons de réordonnancement et à la protection contre des attaques de sécurité basées sur la synchronisation. Un processeur peut avoir des unités fonctionnelles configurées pour exécuter des instructions dans le désordre, un tampon de réordonnancement configuré pour mettre en mémoire tampon les résultats d'exécution d'instructions pour une sortie dans l'ordre, et un dispositif de commande configuré pour rendre aléatoire la synchronisation de données dans le tampon de réordonnancement. Par exemple, le dispositif de commande peut effectuer des ajustements aléatoires sur la capacité du tampon de réordonnancement concernant la mise en mémoire tampon et/ou le tri des résultats d'exécution et ainsi rendre aléatoire la synchronisation des données dans le tampon de réordonnancement.
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