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1. WO2020117645 - A METHOD OF REDUCING EFFECTIVE OXIDE THICKNESS IN A SEMICONDUCTOR STRUCTURE

Publication Number WO/2020/117645
Publication Date 11.06.2020
International Application No. PCT/US2019/063943
International Filing Date 02.12.2019
IPC
H01L 21/67 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/02 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
CPC
H01L 21/0217
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02107Forming insulating materials on a substrate
02109characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
02112characterised by the material of the layer
02123the material containing silicon
0217the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
H01L 21/02205
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02107Forming insulating materials on a substrate
02109characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
02205the layer being characterised by the precursor material for deposition
H01L 21/02247
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02107Forming insulating materials on a substrate
02225characterised by the process for the formation of the insulating layer
02227formation by a process other than a deposition process
02247formation by nitridation, e.g. nitridation of the substrate
H01L 21/31111
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
3105After-treatment
311Etching the insulating layers ; by chemical or physical means
31105Etching inorganic layers
31111by chemical means
Applicants
  • APPLIED MATERIALS, INC. [US]/[US]
Inventors
  • LI, Luping
  • CHEN, Shih Chung
  • DAITO, Kazuya
  • DONG, Lin
  • CHEN, Zhebo
  • YANG, Yixiong
  • HUNG, Steven
Agents
  • KRENICKY, Michael W.
  • TABOADA, Alan
  • LINARDAKIS, Leonard P.
  • MOSER, JR., Raymond R.
Priority Data
16/699,71201.12.2019US
62/775,21804.12.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) A METHOD OF REDUCING EFFECTIVE OXIDE THICKNESS IN A SEMICONDUCTOR STRUCTURE
(FR) PROCÉDÉ DE RÉDUCTION D'ÉPAISSEUR D'OXYDE EFFICACE DANS UNE STRUCTURE SEMI-CONDUCTRICE
Abstract
(EN)
Methods and apparatus for forming a semiconductor structure with a scaled effective oxide thickness is disclosed. In embodiments, a method includes depositing amorphous silicon capping layer having a first surface atop a first surface of a titanium nitride (TiN) layer, wherein the titanium nitride layer is atop a first surface of a high-k dielectric layer disposed within a film stack; contacting the first surface of the amorphous silicon capping layer with a nitrogen containing gas; and annealing the film stack.
(FR)
L'invention concerne des procédés et un appareil permettant de former une structure semi-conductrice avec une épaisseur d'oxyde efficace mise à l'échelle. Selon des modes de réalisation, un procédé consiste à déposer une couche de recouvrement de silicium amorphe ayant une première surface au-dessus d'une première surface d'une couche de nitrure de titane (TiN), la couche de nitrure de titane se trouvant au-dessus d'une première surface d'une couche diélectrique à constante k élevée disposée à l'intérieur d'un empilement de films ; à mettre en contact la première surface de la couche de recouvrement de silicium amorphe avec un gaz contenant de l'azote ; et à recuire l'empilement de films.
Also published as
Latest bibliographic data on file with the International Bureau