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1. WO2020117576 - SUPERCONDUCTING CIRCUITS AND METHODS FOR LATCHING DATA

Publication Number WO/2020/117576
Publication Date 11.06.2020
International Application No. PCT/US2019/063483
International Filing Date 27.11.2019
IPC
H03K 3/38 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
3Circuits for generating electric pulses; Monostable, bistable or multistable circuits
02Generators characterised by the type of circuit or by the means used for producing pulses
38by the use, as active elements, of superconductive devices
H03K 19/195 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02using specified components
195using superconductive devices
H03K 5/1534 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
5Manipulation of pulses not covered by one of the other main groups of this subclass
153Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
1534Transition or edge detectors
H03K 5/00 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
5Manipulation of pulses not covered by one of the other main groups of this subclass
CPC
H01L 39/12
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
39Devices using superconductivity; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
02Details
12characterised by the material
H01L 39/223
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
39Devices using superconductivity; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
22Devices comprising a junction of dissimilar materials, e.g. Josephson-effect devices
223Josephson-effect devices
H03K 19/195
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
195using superconductive devices
H03K 2005/00019
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
5Manipulating of pulses not covered by one of the other main groups of this subclass
00013Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
00019Variable delay
H03K 2005/00234
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
5Manipulating of pulses not covered by one of the other main groups of this subclass
00013Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
0015Layout of the delay element
00234using circuits having two logic levels
H03K 3/38
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
3Circuits for generating electric pulses; Monostable, bistable or multistable circuits
02Generators characterised by the type of circuit or by the means used for producing pulses
38by the use, as active elements, of superconductive devices
Applicants
  • MICROSOFT TECHNOLOGY LICENSING, LLC [US]/[US]
Inventors
  • BRAUN, Alexander L.
Agents
  • MINHAS, Sandip S.
  • CHEN, Wei-Chen Nicholas
  • HINOJOSA-SMITH, Brianna L.
  • SWAIN, Cassandra T.
  • WONG, Thomas S.
  • CHOI, Daniel
  • HWANG, William C.
  • WIGHT, Stephen A.
  • CHATTERJEE, Aaron C.
  • JARDINE, John S.
  • GOLDSMITH, Micah P.
  • TRAN, Kimberly
  • ADJEMIAN, Monica
  • BARKER, Doug
  • CHURNA, Timothy
  • DINH, Phong
  • EVANS, Patrick
  • GABRYJELSKI, Henry
  • GUPTA, Anand
  • LEE, Sunah
  • LEMMON, Marcus
  • MARQUIS, Thomas
  • MEYERS, Jessica
  • ROPER, Brandon
  • SPELLMAN, Steven
  • SULLIVAN, Kevin
  • TABOR, Ben
  • WALKER, Matt
  • WISDOM, Gregg
  • WONG, Ellen
  • ZHANG, Hannah
Priority Data
16/210,12105.12.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SUPERCONDUCTING CIRCUITS AND METHODS FOR LATCHING DATA
(FR) CIRCUITS SUPRACONDUCTEURS ET PROCÉDÉS DE VERROUILLAGE DE DONNÉES
Abstract
(EN)
Superconducting circuits and methods for latching data are described. An example superconducting circuit includes an edge detect circuit (110) configured to receive a logical clock signal (LCLKIN) and generate a return-to-zero clock signal (LCLKRZ). The superconducting circuit further includes a first latch (120) configured to receive the logical clock signal and an input data signal (IN), where the first latch is further configured to selectively delay the input data signal to generate a delayed data signal. The superconducting circuit further includes a second latch (130) configured to receive the return-to-zero clock signal and the delayed data signal, where the second latch is further configured to capture a logical high value corresponding to the input data signal in response to a rising edge of the return-to-zero clock signal and capture a low logical value corresponding to the input data signal in response to a falling edge of the return-to-zero clock signal.
(FR)
La présente invention concerne des circuits supraconducteurs et des procédés pour verrouiller des données. Un exemple de circuit supraconducteur comprend un circuit de détection périphérique (110) conçu pour recevoir un signal d'horloge logique (LCLKIN) et générer un signal d'horloge de retour à zéro (LCLKRZ). Le circuit supraconducteur comprend en outre un premier verrou (120) conçu pour recevoir le signal d'horloge logique et un signal de données d'entrée (IN), le premier verrou étant en outre conçu pour retarder sélectivement le signal de données d'entrée afin de générer un signal de données retardé. Le circuit supraconducteur comprend en outre un second verrou (130) conçu pour recevoir le signal d'horloge de retour à zéro et le signal de données retardé, le second verrou étant en outre conçu pour capturer une valeur logique élevée correspondant au signal de données d'entrée en réponse à un front montant du signal d'horloge de retour à zéro et capturer une valeur logique faible correspondant au signal de données d'entrée en réponse à un front descendant du signal d'horloge de retour à zéro.
Also published as
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