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1. WO2020117568 - DIRECT-INPUT REDUNDANCY SCHEME WITH ADAPTIVE SYNDROME DECODER

Publication Number WO/2020/117568
Publication Date 11.06.2020
International Application No. PCT/US2019/063393
International Filing Date 26.11.2019
IPC
G06F 11/10 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 29/52 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
52Protection of memory contents; Detection of errors in memory contents
H03M 13/15 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
13Linear codes
15Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem codes
CPC
G06F 11/1068
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1008in individual solid state devices
1068in sector programmable memories, e.g. flash disk
G11C 29/52
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
52Protection of memory contents; Detection of errors in memory contents
H03M 13/45
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
37Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
45Soft decoding, i.e. using symbol reliability information
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • NAKAI, Kiyoshi
Agents
  • HARRIS, Philip
Priority Data
16/212,01706.12.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) DIRECT-INPUT REDUNDANCY SCHEME WITH ADAPTIVE SYNDROME DECODER
(FR) MÉCANISME DE REDONDANCE À ENTRÉE DIRECTE AVEC DÉCODEUR DE SYNDROME ADAPTATIF
Abstract
(EN)
Methods, systems, and devices for operating memory cell(s) using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. An output of the error correction circuit may be used to generate syndrome bits, which may be decoded by a syndrome decoder. The syndrome decoder may indicate whether a bit of the data should be corrected by selectively reacting to inputs based on the type of data to be corrected. For example, the syndrome decoder may react to a first set of inputs if the data bit to be corrected is a regular data bit, and react to a second set of inputs if the data bit to be corrected is a redundant data bit.
(FR)
L'invention concerne des procédés, des systèmes et des dispositifs pour faire fonctionner une ou plusieurs cellules de mémoire à l'aide d'un mécanisme de redondance de colonnes à entrée directe. Un dispositif qui a lu des données dans des plans de données peut remplacer des données d'un des plans par des données de redondance issues d'un plan de données stockant des données de redondance. Le dispositif peut ensuite fournir les données de redondance à un circuit de correction d'erreurs couplé au plan de données qui stockait les données de redondance. Une sortie du circuit de correction d'erreurs peut être utilisée pour générer des bits de syndrome, qui peuvent être décodés par un décodeur de syndrome. Le décodeur de syndrome peut indiquer si un bit des données doit être corrigé par réaction sélective à des entrées sur la base du type de données à corriger. Par exemple, le décodeur de syndrome peut réagir à un premier ensemble d'entrées si le bit de données à corriger est un bit de données ordinaire, et réagir à un second ensemble d'entrées si le bit de données à corriger est un bit de données redondant.
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