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1. WO2020117567 - DIRECT-INPUT REDUNDANCY SCHEME WITH DEDICATED ERROR CORRECTION CODE CIRCUIT

Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

[ EN ]

CLAIMS

What is claimed is:

1. An apparatus, comprising:

data planes coupled with a word line and configured to store data bits;

error correction code (ECC) circuits each configured to receive data from a respective data plane of the data planes;

a redundant data plane coupled with the word line and configured to store redundant data corresponding to data stored by at least one of the data planes; and

a redundant ECC circuit coupled with the redundant data plane and configured to receive redundant data from the redundant data plane.

2. The apparatus of claim 1, further comprising:

a first logic gate coupled with the ECC circuits and configured to receive a result of a bitwise operation on data bits from select data planes of the data planes; and

a conductive path between an output of the redundant ECC circuit and an input of the first logic gate.

3. The apparatus of claim 2, further comprising:

a second logic gate coupled with the redundant ECC circuit and comprising a portion of the conductive path, the second logic gate configured to selectively transfer to the first logic gate a result of a bitwise operation on the redundant data.

4. The apparatus of claim 1, further comprising:

digit lines each coupled with a respective data plane and a respective ECC circuit; and

at least one digit line coupled with the redundant data plane and the redundant

ECC circuit.

5. The apparatus of claim 1, wherein the redundant ECC circuit comprises a set of logic gates configured to perform bitwise operations on the redundant data, and wherein the ECC circuits comprise sets of logic gates configured to perform bitwise operations on data from the data planes.

6. The apparatus of claim 1, wherein the redundant data comprises data representing logic states that are a basis for the data bits stored in the at least one data plane.

7. An apparatus, comprising:

a redundant data plane configured to store redundant data that corresponds to data stored by least a first data plane of a set of data planes;

a redundant error correction code (ECC) circuit coupled with the redundant data plane via digit lines and configured to perform an exclusive-OR (XOR) operation on redundant data received from the redundant data plane; and

an AND logic gate coupled with an output of the redundant ECC circuit and configured to output a signal representative of a result of the XOR operation on the redundant data based at least in part on a control signal.

8. The apparatus of claim 7, further comprising:

a logic gate configured to drive the AND logic gate in response to the control signal.

9. The apparatus of claim 8, wherein the logic gate comprises an OR logic gate.

10. The apparatus of claim 7, further comprising:

an XOR logic gate coupled with a subset of the set of data planes and an output of the AND logic gate.

11. The apparatus of claim 7, wherein the control signal indicates that the redundant data corresponds to data stored by the first data plane.

12. A method, comprising:

selecting data planes that are each coupled with a respective error correction code (ECC) circuit, wherein the selected data planes include a first data plane;

transferring data from multiple data planes of the selected data planes to the respective ECC circuits of the multiple data planes;

transferring redundant data for the first data plane from a redundant data plane to a redundant ECC circuit coupled with the redundant data plane, the redundant data corresponding to data stored by the first data plane; and

generating syndrome bits for a codeword comprising the data and the redundant data based at least in part on outputs of the respective ECC circuits of the multiple data planes and an output of the redundant ECC circuit.

13. The method of claim 12, further comprising:

performing ECC operations on the data transferred from the multiple data planes, wherein the outputs of the ECC circuits are based at least in part on the ECC operations; and

performing an ECC operation on the redundant data transferred from the redundant data plane, wherein the output of the redundant ECC circuit is based at least in part on the ECC operation on the redundant data.

14. The method of claim 12, further comprising:

transferring the data from the multiple data planes concurrent with transferring the redundant data from the redundant data plane.

15. The method of claim 12, further comprising:

decoding the syndrome bits; and

inverting a bit of the codeword based at least in part on a result of decoding the syndrome bits.

16. The method of claim 12, wherein transferring the redundant data to the redundant ECC circuit comprises:

refraining from transferring the redundant data to the respective ECC circuit for the first data plane.

17. The method of claim 12, wherein transferring the data from the multiple data planes comprises:

refraining from transferring the data stored by the first data plane to the respective ECC circuit.

18. The method of claim 17, further comprising:

inputting null data into the respective ECC circuit for the first data plane; and performing an ECC operation on the null data.

19. The method of claim 12, further comprising:

applying a voltage to a word line coupled with the data planes and the redundant data, wherein the data planes and the redundant data plane are selected based at least in part on applying the voltage.

20. A method, comprising:

performing, using an error correction code (ECC) circuit, a first bitwise operation on a first set of redundant data that corresponds to data stored by a first data plane;

transferring a result of the first bitwise operation to a first set of logic gates based at least in part on the redundant data corresponding to data stored by the first data plane;

performing, using the ECC circuit, a second bitwise operation on a second set of redundant data that corresponds to data stored by a second data plane; and

transferring a result of the second bitwise operation to a second set of logic gates different from the first set of logic gates based at least in part on the redundant data corresponding to data stored by the second data plane.

21. The method of claim 20, further comprising:

generating, for a first codeword, a first set of syndrome bits based at least in part on the result of the first bitwise operation, the first codeword comprising the data stored by the first data plane; and

generating, for a second codeword, a second set of syndrome bits based at least in part on the result of the second bitwise operation, the second codeword comprising the data stored by the second data plane.

22. The method of claim 20, further comprising:

receiving a first control signal indicating that the first set of redundant data corresponds to data stored by the first data plane; and

transferring the result of the first bitwise operation based at least in part on the first control signal.

23. The method of claim 22, further comprising:

receiving a second control signal indicating that the second set of redundant data corresponds to data stored by the second data plane; and

transferring the result of the second bitwise operation based at least in part on the second control signal.

24. The method of claim 20, wherein the first bitwise operation and the second bitwise operation each comprise an exclusive-OR operation.