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1. WO2020117566 - MULTI-LEVEL SIGNALING FOR A MEMORY DEVICE

Publication Number WO/2020/117566
Publication Date 11.06.2020
International Application No. PCT/US2019/063382
International Filing Date 26.11.2019
IPC
G06F 11/10 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 29/52 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
52Protection of memory contents; Detection of errors in memory contents
CPC
G11C 29/10
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
10Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
G11C 29/56
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
56External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
G11C 29/56004
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
56External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
56004Pattern generation
H04L 1/0003
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
1Arrangements for detecting or preventing errors in the information received
0001Systems modifying transmission characteristics according to link quality, e.g. power backoff
0002by adapting the transmission rate
0003by switching between different modulation schemes
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • SPIRKL, Wolfgang, Anton
  • RICHTER, Michael, Dieter
  • HEIN, Thomas
  • MAYER, Peter
  • BROX, Martin
Agents
  • HARRIS, Philip
Priority Data
16/681,58712.11.2019US
62/776,08906.12.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) MULTI-LEVEL SIGNALING FOR A MEMORY DEVICE
(FR) SIGNALISATION À MULTIPLES NIVEAUX POUR UN DISPOSITIF DE MÉMOIRE
Abstract
(EN)
Methods, systems, and devices for testing of multi-level signaling associated with a memory device are described. A tester may be used to test one or more operations of a memory device. The memory device may be configured to communicate data using a modulation scheme that includes three or more symbols. The tester may be configured to communicate data using a modulation scheme that includes three or fewer symbols. Techniques for testing the memory device using such a tester are described.
(FR)
L'invention concerne des procédés, des systèmes et des dispositifs de test de signalisation à multiples niveaux associée à un dispositif de mémoire. Un testeur peut être utilisé pour tester une ou plusieurs opérations d'un dispositif de mémoire. Le dispositif de mémoire peut être configuré pour communiquer des données en utilisant un schéma de modulation qui contient au moins trois symboles. Le testeur peut être configuré pour communiquer des données en utilisant un schéma de modulation qui contient trois symboles ou moins. L'invention concerne également des techniques de test du dispositif de mémoire à l'aide d'un tel testeur.
Also published as
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