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1. WO2020117388 - ACCELERATING DATAFLOW SIGNAL PROCESSING APPLICATIONS ACROSS HETEROGENEOUS CPU/GPU SYSTEMS

Publication Number WO/2020/117388
Publication Date 11.06.2020
International Application No. PCT/US2019/057796
International Filing Date 24.10.2019
IPC
G06F 9/50 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
50Allocation of resources, e.g. of the central processing unit
G06F 9/54 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
54Interprogram communication
G06F 9/52 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
52Program synchronisation; Mutual exclusion, e.g. by means of semaphores
CPC
G06F 9/485
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
48Program initiating; Program switching, e.g. by interrupt
4806Task transfer initiation or dispatching
4843by program, e.g. task dispatcher, supervisor, operating system
485Task life-cycle, e.g. stopping, restarting, resuming execution
G06F 9/4881
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
48Program initiating; Program switching, e.g. by interrupt
4806Task transfer initiation or dispatching
4843by program, e.g. task dispatcher, supervisor, operating system
4881Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
G06F 9/5016
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
50Allocation of resources, e.g. of the central processing unit [CPU]
5005to service a request
5011the resources being hardware resources other than CPUs, Servers and Terminals
5016the resource being the memory
G06F 9/5066
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
50Allocation of resources, e.g. of the central processing unit [CPU]
5061Partitioning or combining of resources
5066Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
G06F 9/5077
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
50Allocation of resources, e.g. of the central processing unit [CPU]
5061Partitioning or combining of resources
5077Logical partitioning of resources; Management or configuration of virtualized resources
G06F 9/522
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
52Program synchronisation; Mutual exclusion, e.g. by means of semaphores
522Barrier synchronisation
Applicants
  • RAYTHEON COMPANY [US]/[US]
Inventors
  • CHAMPIGNY, Michael
Agents
  • DURKEE, Paul, D.
  • DALY, Christopher, S.
  • DIMOV, Kiril, O.
  • MOFFORD, Donald, F.
  • ROBINSON, Kermit
  • MOOSEY, Anthony, T.
  • CROWLEY, Judith, C.
  • DOWNING, Marianne, M.
  • BLAU, David, E.
  • DUBUC, Marisa, J.
  • LANGE, Kristoffer, W.
Priority Data
16/372,61802.04.2019US
62/776,11906.12.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) ACCELERATING DATAFLOW SIGNAL PROCESSING APPLICATIONS ACROSS HETEROGENEOUS CPU/GPU SYSTEMS
(FR) ACCÉLÉRATION D'APPLICATIONS DE TRAITEMENT DE SIGNAL DE FLUX DE DONNÉES À TRAVERS DES SYSTÈMES CPU/GPU HÉTÉROGÈNES
Abstract
(EN)
A method includes: forming a virtual tile cluster having tiles, wherein a tile comprises a processor and memory from a CPU device and a GPU device, and a tile in the GPU device further comprises subprocessors; forming a virtual unified memory that is accessible by the CPU and GPU devices; receiving a task; assigning the task to a tile of the virtual tile cluster according to a pre-defined rule. When the task is assigned to a tile in the GPU device, the method further performs: broadcasting the task to the subprocessors of a tile using a GPU shuffle instruction; and dividing data for the task and assigning the divided data to the subprocessors, wherein each subprocessor runs a codelet using the each of divided data. The task is executed by the at least one tile of the virtual tile cluster.
(FR)
L’invention concerne un procédé qui consiste à : former une grappe de pavés virtuels comprenant des pavés, un pavé comprenant un processeur et une mémoire à partir d'un dispositif CPU et d'un dispositif GPU, et un pavé dans le dispositif GPU comprenant en outre des sous-processeurs ; la formation d'une mémoire unifiée virtuelle qui est accessible par les dispositifs CPU et GPU ; la réception d'une tâche ; l'attribution de la tâche à un pavé de la grappe de pavés virtuels selon une règle prédéfinie. Lorsque la tâche est attribuée à un pavé dans le dispositif GPU, le procédé réalise en outre : la diffusion de la tâche vers les sous-processeurs d'un pavé à l'aide d'une instruction de réarrangement de GPU ; et la division de données pour la tâche et l'attribution des données divisées aux sous-processeurs, chaque sous-processeur exécutant un codelet à l'aide de chacune des données divisées. La tâche est exécutée par le ou les pavés de la grappe de pavés virtuels.
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