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1. WO2020117330 - FINFET-BASED SPLIT GATE NON-VOLATILE FLASH MEMORY WITH EXTENDED SOURCE LINE FINFET, AND METHOD OF FABRICATION

Publication Number WO/2020/117330
Publication Date 11.06.2020
International Application No. PCT/US2019/046306
International Filing Date 13.08.2019
IPC
H01L 27/11524 2017.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
11521characterised by the memory core region
11524with cell select transistors, e.g. NAND
H01L 29/66 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
CPC
G11C 16/0408
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
0408comprising cells containing floating gate transistors
G11C 16/10
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
10Programming or data input circuits
G11C 16/14
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
10Programming or data input circuits
14Circuits for erasing electrically, e.g. erase voltage switching circuits
G11C 16/26
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
26Sensing or reading circuits; Data output circuits
H01L 21/0271
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
0271comprising organic layers
H01L 21/3081
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
302to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
306Chemical or electrical treatment, e.g. electrolytic etching
308using masks
3081characterised by their composition, e.g. multilayer masks, materials
Applicants
  • SILICON STORAGE TECHNOLOGY, INC. [US]/[US]
Inventors
  • JOURBA, Serguei
  • DECOBERT, Catherine
  • ZHOU, Feng
  • KIM, Jinho
  • LIU, Xian
  • DO, Nhan
Agents
  • LIMBACH, Alan, A.
Priority Data
16/208,28803.12.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) FINFET-BASED SPLIT GATE NON-VOLATILE FLASH MEMORY WITH EXTENDED SOURCE LINE FINFET, AND METHOD OF FABRICATION
(FR) MÉMOIRE FLASH NON VOLATILE À DOUBLE GRILLE BASÉE SUR UN FINFET COMPRENANT UN FINFET À LIGNE DE SOURCE ÉTENDUE, ET PROCÉDÉ DE FABRICATION
Abstract
(EN)
A memory cell is formed on a semiconductor substrate having an upper surface with a plurality of upwardly extending fins. First and second fins extend in one direction, and a third fin extends in an orthogonal direction. Spaced apart source and drain regions are formed in each of the first and second fins, defining a channel region extending there between in each of the first and second fins. The source regions are disposed at intersections between the third fin and the first and second fins. A floating gate is disposed laterally between the first and second fins, and laterally adjacent to the third fin, and extends along first portions of the channel regions. A word line gate extends along second portions of the channel regions. A control gate is disposed over the floating gate. An erase gate is disposed over the source regions and the floating gate.
(FR)
La présente invention porte sur une cellule de mémoire formée sur un substrat semi-conducteur comportant une surface supérieure pourvue d'une pluralité d'ailettes s'étendant vers le haut. Des première et deuxième ailettes s'étendent dans une direction, et une troisième ailette s'étend dans une direction orthogonale. Des régions de source et de drain espacées les unes des autres sont formées dans la première ailette et dans la seconde ailette, délimitant une région de canal s'étendant entre elles dans chacune des première et deuxième ailettes. Les régions de source sont disposées au niveau d'intersections entre la troisième ailette et les première et deuxième ailettes. Une grille flottante est disposée latéralement entre les première et deuxième ailettes, et latéralement adjacente à la troisième ailette, et s'étend le long de premières parties des régions de canal. Une grille de ligne de mots s'étend le long de secondes parties des régions de canal. Une grille de commande est disposée au-dessus de la grille flottante. Une grille d'effacement est disposée au-dessus des régions de source et de la grille flottante.
Also published as
Latest bibliographic data on file with the International Bureau