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1. WO2020116449 - SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

Publication Number WO/2020/116449
Publication Date 11.06.2020
International Application No. PCT/JP2019/047234
International Filing Date 03.12.2019
IPC
H01L 23/00 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
H01L 23/58 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
58Structural electrical arrangements for semiconductor devices not otherwise provided for
H01L 27/14 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
CPC
H01L 2224/05547
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05541Structure
05547comprising a core and a coating
H01L 2224/05623
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05599Material
056with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05617the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
05623Magnesium [Mg] as principal constituent
H01L 2224/05624
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05599Material
056with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05617the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
05624Aluminium [Al] as principal constituent
H01L 2224/05647
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05599Material
056with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05638the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
05647Copper [Cu] as principal constituent
H01L 2224/05649
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05599Material
056with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05638the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
05649Manganese [Mn] as principal constituent
H01L 2224/08121
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
07Structure, shape, material or disposition of the bonding areas after the connecting process
08of an individual bonding area
081Disposition
0812the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
08121the connected bonding areas being not aligned with respect to each other
Applicants
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION [JP]/[JP]
Inventors
  • MITSUHASHI Ikue
  • IWAFUCHI Toshiaki
Agents
  • WATANABE Kaoru
Priority Data
2018-22749804.12.2018JP
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET DISPOSITIF ÉLECTRONIQUE
Abstract
(EN)
A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, and at least one guard structure including a first guard element, a second guard element, and a third guard element. The first semiconductor substrate and the second semiconductor substrate are bonded to one another at a bonding interface between a surface of the first semiconductor substrate and a surface of the second semiconductor substrate. The first guard element is in the first semiconductor substrate and spaced apart from the third guard element by a portion of the first semiconductor substrate. The second guard element is in the second semiconductor substrate and spaced apart from the third guard element by a portion of the second semiconductor substrate, and the third guard element includes portions in the first surface and the second surface to bond the first semiconductor substrate to the second semiconductor substrate.
(FR)
L'invention concerne un dispositif à semi-conducteur comprenant un premier substrat semi-conducteur, un second substrat semi-conducteur, et au moins une structure de protection comprenant un premier élément de protection, un deuxième élément de protection et un troisième élément de protection. Le premier substrat semi-conducteur et le second substrat semi-conducteur sont liés l'un à l'autre au niveau d'une interface de liaison entre une surface du premier substrat semi-conducteur et une surface du second substrat semi-conducteur. Le premier élément de protection est dans le premier substrat semi-conducteur et espacé du troisième élément de protection par une partie du premier substrat semi-conducteur. Le deuxième élément de protection est dans le second substrat semi-conducteur et espacé du troisième élément de protection par une partie du second substrat semi-conducteur, et le troisième élément de protection comprend des parties dans la première surface et la seconde surface pour lier le premier substrat semi-conducteur au second substrat semi-conducteur.
Also published as
Latest bibliographic data on file with the International Bureau