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1. WO2020115766 - STACKED BUFFER IN TRANSISTORS

Publication Number WO/2020/115766
Publication Date 11.06.2020
International Application No. PCT/IN2019/050886
International Filing Date 05.12.2019
IPC
H01L 29/778 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
778with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/06 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02Semiconductor bodies
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/12 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02Semiconductor bodies
12characterised by the materials of which they are formed
H01L 21/335 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334Multistep processes for the manufacture of devices of the unipolar type
335Field-effect transistors
Applicants
  • INDIAN INSTITUTE OF SCIENCE [IN]/[IN]
Inventors
  • RAGHAVAN, Srinivasan
  • BHAT, Navakanta
  • SOMAN, Rohith
Agents
  • LAKSHMIKUMARAN, Malathi
  • PHILLIPS, Prashant
  • RAE, Konpal
  • PANDEYA, Jaya
  • SRINIVASAN, T.
Priority Data
20184104648107.12.2018IN
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) STACKED BUFFER IN TRANSISTORS
(FR) TAMPONS EMPILÉS DANS DES TRANSISTORS
Abstract
(EN)
The present subject matter provides a High Mobility Electron Transistor (HEMT) (200, 300, 400) comprising: a substrate (202), a nucleation layer (204) provided on the substrate, a channel layer (214), and a buffer layer (208) formed between the nucleation layer (204) and the channel layer (214). The buffer layer (208) comprises a vertical stack of p-n junctions. Each p-n junction of the vertical stack of p-n junctions comprises an n-type layer (212b) provided on a p-type layer (212a). The n-type layer (212b) and the p-type layer (212a) are parallel to the substrate.
(FR)
La présente invention concerne un transistor à haute mobilité électronique (HEMT) (200, 300, 400) comprenant : un substrat (202), une couche de nucléation (204) disposée sur le substrat, une couche de canal (214), et une couche tampon (208) formée entre la couche de nucléation (204) et la couche de canal (214). La couche tampon (208) comprend un empilement vertical de jonctions p-n. Chaque jonction p-n de l'empilement vertical de jonctions p-n comprend une couche de type n (212b) disposée sur une couche de type p (212a). La couche de type n (212b) et la couche de type p (212a) sont parallèles au substrat.
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