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1. WO2020114799 - CONTROLLED NOT GATE PARALLELIZATION IN QUANTUM COMPUTING SIMULATION

Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

[ EN ]

CLAIMS

1. A system, comprising:

a memory that stores computer executable components; and

a processor that executes the computer executable components stored in the memory, wherein the computer executable components comprise:

a replication component that simulates a controlled NOT gate during a qubit-reordering; and

a parallelization component that performs memory access balancing based on the controlled NOT gate being simulated by the replication component during the qubit-reordering.

2. The system of claim 1 , wherein the computer executable components further comprise

a selector component that selects a first bit and a second bit for the qubit-reordering, wherein the first bit is a control bit.

3. The system of claim 2, wherein the selector component selects the first bit based on a determination that the first bit is a bit that is equal to or higher than a sum comprising a number of qubits less a binary logarithm (log2) of a number of non-uniform memory access nodes.

4. The system of claim 2, wherein the selector component selects the first bit based on a determination that the first bit is a bit that is less a binary logarithm (log2) of a number of non-uniform memory access nodes.

5. The system of claim 2, wherein the selector component selects the second bit based on a determination that the second bit is different from the first bit and is not a target bit with the first bit as the control bit.

6. The system of claim 1 wherein the computer executable components further comprise:

an arrangement component that implements the qubit-reordering for quantum computing, wherein the arrangement component reorders a first bit with a second bit.

7. The system of claim 1 , wherein the computer executable components further comprise:

a reversal component that reverts the qubit-reordering based on an evaluation component determining a lack of memory access improvement.

8. The system of claim 1 , wherein the qubit-reordering minimizes fragmented access of a quantum memory.

9. The system of claim 1 , wherein the qubit-reordering minimizes a thread locality.

10. The system of claim 1 , wherein the qubit-reordering is a first qubit-reordering, and wherein the replication

component simulates the controlled NOT gate during a second qubit reordering based on a determination by an evaluation component that the memory access balancing was successful.

11. A computer-implemented method, comprising:

simulating, by a system operatively coupled to a processor, a controlled NOT gate during a qubitreordering; and

performing, by the system, a memory access balancing based on the simulating the controlled NOT gate during the qubit-reordering.

12. The computer-implemented method of claim 11 , further comprising:

selecting, by the system, a first bit and a second bit for the qubit-reordering, wherein the first bit is a control bit.

13. The computer-implemented method of claim 12, wherein the selecting the first bit comprises selecting the first bit based on a determination that the first bit is a bit that is equal to or higher than a sum comprising a number of qubits less a binary logarithm (log2) of a number of non-uniform memory access nodes.

14. The computer-implemented method of claim 12, wherein the selecting the first bit comprises selecting the first bit based on a determination that the first bit is a bit that is less a binary logarithm (log2) of a number of non-uniform memory access nodes.

15. The computer-implemented method of claim 12, wherein the selecting the second bit comprises selecting the second bit based on a determination that the second bit is different from the first bit and is not a target bit with the first bit as the control bit.

16. The computer-implemented method of claim 11 , further comprising reverting, by the system, the qubitreordering based on a determination of a lack of memory access improvement.

17. The computer-implemented method of claim 11 , wherein the qubit-reordering is a first qubit-reordering, and wherein the computer-implemented method further comprises:

determining, by the system, that the memory access balancing was successful; and

simulating, by the system, the controlled NOT gate during a second qubit reordering based on the determining.

18. A method, comprising:

selecting, by a system operatively coupled to a processor, a first qubit and a second qubit, wherein the first qubit is a control qubit; and

reordering, by the system, the first qubit with the second qubit, wherein a controlled NOT gate is simulated during the reordering.

19. The method of claim 18, wherein the reordering the first qubit with the second qubit comprises minimizing, by the system, an occurrence of one or more control qubits that are equal to or higher than a first quantity of qubits minus a binary logarithm (log2) of a second quantity of non-uniform memory access nodes.

20. The method of claim 18, wherein the reordering the first qubit with the second qubit comprises minimizing, by the system, an occurrence of one or more control qubits that are lower than a binary logarithm (log2) of a quantity of non-uniform memory access nodes.

21. A computer program product that facilitates quantum computing simulation of a controlled NOT gate, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions are executable by a processor to cause the processor to perform the steps of a method as claimed in any of claims 11 to 20.