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1. WO2020114660 - HYBRID SHORT CIRCUIT FAILURE MODE PREFORM FOR POWER SEMICONDUCTOR DEVICES

Note: Text based on automatic Optical Character Recognition processes. Please use the PDF version for legal matters

[ EN ]

Claims

1. A power semiconductor module, comprising:

a base plate (1) having a top surface and a bottom surface;

a semiconductor chip (2) having a bottom surface and a top surface, the semiconductor chip (2) being disposed on the top surface of the base plate (1), the bottom surface of the semiconductor chip (2) being in contact with the top surface of the base plate (1), the semiconductor chip (2) including a wide-bandgap semiconductor material;

a preform (3) having a bottom surface and a top surface, the preform (3) being disposed on the top surface of the semiconductor chip (2), the bottom surface of the preform (3) being in contact with the top surface of the semiconductor chip (2);

a pressing element (4) in contact with the top surface of the preform (3) and configured to apply a pressure onto the top surface of the preform (3),

characterized in that the preform (3) comprises a first electrically conductive layer

(6) and a second electrically conductive layer (5),

the first electrically conductive layer (6) has at least one protrusion (7) protruding towards the top surface of the semiconductor chip (2) and defining at least one recess (9) in the first electrically conductive layer (6) of the preform (3),

the at least one protrusion (7) and the first electrically conductive layer (6) are made from the same material or from different materials,

at least a portion of the second electrically conductive layer (5) is positioned in the recess (9) and on the top surface of the semiconductor chip (2),

the material of the at least one protrusion (7) has a higher melting point than the material of the second electrically conductive layer (5), and

the power semiconductor module is configured so that in an event of semiconductor chip failure with heat dissipation, the at least one protrusion (7) of the first electrically conductive layer (6) penetrates through residual material (8) of the semiconductor chip (2) upon pressure applied by the pressing element (4) towards the base plate (1) so as to establish a contact between the at least one protrusion (7) of the first electrically conductive layer (7) and the base plate (1) and form a short circuit bridging the defective semiconductor chip (2) in a short circuit failure mode.

2. The power semiconductor module according to claim 1, wherein the pressing element (4) is in laminar contact with the top surface of the preform (3); the bottom surface of the preform (3) is in laminar contact with the top surface of the semiconductor chip (2); and the bottom surface of the semiconductor chip (2) is in laminar contact with the top surface of the base plate (1) and attached to the base plate (1).

3. The power semiconductor module according to one of the preceding claims, wherein the at least one protrusion (3) is laterally surrounded by the second electrically conductive layer (5).

4. The power semiconductor module according to one of the preceding claims, wherein the bottom surface of the preform (3) is formed by a bottom surface of the second electrically conductive layer (5).

5. The power semiconductor module according to one of the preceding claims, wherein the bottom surface of the preform (3) is formed by a bottom surface of the second electrically conductive layer (5) and a bottom surface of the protrusion (7).

6. The power semiconductor module according to one of the preceding claims, wherein the semiconductor chip (2) comprises a semiconductor layer and a metallization layer on the semiconductor layer at the top surface of the semiconductor chip (2), wherein the metallization layer is in direct contact with the preform (3) and with the semiconductor layer, and wherein a contact area between the metallization layer and the semiconductor layer defines an active area of the semiconductor chip (2).

7. The power semiconductor module according to claim 6, wherein a size of a contact area between the bottom surface of the preform (3) and the top surface of the semiconductor chip (2) is at least 50 %, exemplarily at least 80 %, or exemplarily at least 90 % of a size of an active area of the semiconductor chip (2); and less than 100 %, exemplarily less than 98 %, or exemplarily less than 95 % of the size of the active area of the semiconductor chip (2).

8. The power semiconductor module according to claim 6 or 7,

wherein a size of the bottom surface of the at least one protrusion (7) is less than 60 %, exemplarily less than 30 %, or exemplarily less than 10 % of a size of the active area of the semiconductor chip (2).

9. The power semiconductor module according to one of the preceding claims, wherein the material of the first electrically conductive layer (6) has a melting point of above 1500°C, exemplarily above 2000°C, or exemplarily above 2500°C, and the material of the second electrically conductive layer (5) has a melting point below 1500°C, exemplarily below 1200°C, or exemplarily below 900°C.

10. The power semiconductor module according to one of the preceding claims, wherein the at least one protrusion (7) has at least one of a vertical, a rounded or an inclined edge (10).

11. The power semiconductor module according to one of the preceding claims, wherein the at least one protrusion (7) has one of a cylindrical shape, a spherical cap shape, or a conical shape.

12. The power semiconductor module according to one of the preceding claims, wherein the first electrically conductive layer (6) comprises one of molybdenum (Mo), tungsten (W) or an alloy thereof.

13. The power semiconductor module according to one of the preceding claims, wherein the material of the second electrically conductive layer (5) comprises one of aluminium (Al), copper (Cu), silver (Ag), gold (Au), tin (Sn), lead (Pb), magnesium (Mg) or an alloy thereof.

14. The power semiconductor module according to one of the preceding claims, wherein the wide-bandgap semiconductor material included in the semiconductor chip (2) comprises silicon carbide (SiC) and/or gallium nitride (GaN).

15. The power semiconductor module according to one of the preceding claims, wherein the preform (3) has a coefficient of thermal expansion which differs from the coefficient of thermal expansion of the semiconductor chip (2) in a range of less than 250 %, in particular less than 50 %.