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1. WO2020114073 - INSULATED GATE BIPOLAR TRANSISTOR AND PREPARATION METHOD THEREFOR, AND ELECTRICAL DEVICE

Publication Number WO/2020/114073
Publication Date 11.06.2020
International Application No. PCT/CN2019/110322
International Filing Date 10.10.2019
IPC
H01L 29/739 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
70Bipolar devices
72Transistor-type devices, i.e. able to continuously respond to applied control signals
739controlled by field effect
H01L 29/06 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02Semiconductor bodies
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/331 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
328Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors
33the devices comprising three or more electrodes
331Transistors
Applicants
  • 珠海格力电器股份有限公司 GREE ELECTRIC APPLIANCES, INC. OF ZHUHAI [CN]/[CN]
Inventors
  • 廖勇波 LIAO, Yongbo
  • 史波 SHI, Bo
  • 肖婷 XIAO, Ting
  • 何昌 HE, Chang
Agents
  • 广州华进联合专利商标代理有限公司 ADVANCE CHINA IP LAW OFFICE
Priority Data
201811464344.203.12.2018CN
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) INSULATED GATE BIPOLAR TRANSISTOR AND PREPARATION METHOD THEREFOR, AND ELECTRICAL DEVICE
(FR) TRANSISTOR BIPOLAIRE À GRILLE ISOLÉE ET SON PROCÉDÉ DE PRÉPARATION, ET DISPOSITIF ÉLECTRIQUE
(ZH) 绝缘栅双极型晶体管及其制备方法、电气设备
Abstract
(EN)
Provided in the present application are an insulated gate bipolar transistor and a preparation method therefor, and an electrical device, a polycrystalline silicon layer in a trench of the present insulated gate bipolar transistor being etched to form two polycrystalline silicon layers, and an N-type layer and a P-type layer being additionally disposed at the bottom of the trench; the current paths not only comprise the current path of the structure of an insulated gate bipolar transistor having a traditional wide trench, but also the additional trench current of the bottom and side walls of the trench and the current of the PNP structure in the middle of the bottom of the trench; thus, within the same area, the trench in the present application has a stronger current-carrying capacity.
(FR)
La présente invention concerne un transistor bipolaire à grille isolée et son procédé de préparation, et un dispositif électrique, une couche de silicium polycristallin dans une tranchée du transistor bipolaire à grille isolée étant gravée pour former deux couches de silicium polycristallin, et une couche de type N et une couche de type P étant en outre disposées au fond de la tranchée ; les trajets de courant ne comprennent pas seulement le trajet de courant de la structure d'un transistor bipolaire à grille isolée ayant une tranchée large classique, mais également le courant de tranchée supplémentaire des parois inférieure et latérale de la tranchée et le courant de la structure PNP au milieu du fond de la tranchée ; ainsi, dans la même zone, la tranchée dans la présente invention présente une capacité de transport de courant plus forte.
(ZH)
本申请提供了一种绝缘栅双极型晶体管及其制备方法、电气设备,该绝缘栅双极型晶体管在沟槽内的多晶硅层刻蚀形成两个多晶硅层,并且在沟槽的底部增设了N型层以及P型层,电流路径除了具备传统宽沟槽的绝缘栅双极型晶体管的构造的电流路径外,还新增了沟槽底部侧壁的沟道电流,沟道底部中间的PNP结构的电流,因此,在相同的面积下,本申请中的沟槽的通电能力更强。
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Latest bibliographic data on file with the International Bureau