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1. WO2020114054 - INSULATED GATE BIPOLAR TRANSISTOR AND FABRICATION METHOD THEREFOR

Publication Number WO/2020/114054
Publication Date 11.06.2020
International Application No. PCT/CN2019/109000
International Filing Date 29.09.2019
IPC
H01L 29/739 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
70Bipolar devices
72Transistor-type devices, i.e. able to continuously respond to applied control signals
739controlled by field effect
H01L 29/06 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02Semiconductor bodies
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/331 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
328Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors
33the devices comprising three or more electrodes
331Transistors
Applicants
  • 珠海格力电器股份有限公司 GREE ELECTRIC APPLIANCES, INC. OF ZHUHAI [CN]/[CN]
Inventors
  • 史波 SHI, Bo
  • 肖婷 XIAO, Ting
  • 曾丹 ZENG, Dan
  • 廖勇波 LIAO, Yongbo
  • 敖利波 AO, Libo
  • 梁博 LIANG, Bo
Agents
  • 广州华进联合专利商标代理有限公司 ADVANCE CHINA IP LAW OFFICE
Priority Data
201811466031.003.12.2018CN
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) INSULATED GATE BIPOLAR TRANSISTOR AND FABRICATION METHOD THEREFOR
(FR) TRANSISTOR BIPOLAIRE À GRILLE ISOLÉE ET SON PROCÉDÉ DE FABRICATION
(ZH) 绝缘栅双极型晶体管及其制备方法
Abstract
(EN)
Disclosed are an insulated gate bipolar transistor and a fabrication method therefor. The transistor comprises a substrate (1), wherein the substrate (1) is provided with a collector layer (2) and a device layer (3), at least two opposite side edges of the projection of the device layer (3) on the substrate (1) are spaced apart from the edge of the projection of the collector layer (2) on the substrate (1) by a set distance, an outer surface of the device layer (3) is coated with a medium layer (4), one side, away from the device layer (3), of the medium layer (4) forms an emitter bonding metal layer (5), and a collector bonding metal layer (6) is arranged at the position located on the one side, away from the substrate (1), of the collector layer (2) and outside the device layer (3). According to the transistor, when the transistor is electrified, electrons pass through the emitter bonding metal layer (5), the device layer (3), the collector layer (2) and the collector bonding metal layer (6) in sequence to realize electric current conduction, so that a passing path of an electric current does not pass through the substrate (1), a thick substrate (1) can be used in the transistor to bear an ultrathin device layer (3), and an ultrathin thinning process and the related complex steps are not needed, thereby reducing the manufacturing cost and the manufacturing difficulty.
(FR)
L'invention concerne un transistor bipolaire à grille isolée et son procédé de fabrication. Le transistor comprend un substrat (1), le substrat (1) comprenant une couche collectrice (2) et une couche de dispositif (3), au moins deux bords latéraux opposés de la saillie de la couche de dispositif (3) sur le substrat (1) sont espacés du bord de la saillie de la couche de collecteur (2) sur le substrat (1) d'une distance définie, une surface externe de la couche de dispositif (3) est revêtue d'une couche de milieu (4), un côté, à l'opposé de la couche de dispositif (3), de la couche de milieu (4) forme une couche métallique de liaison d'émetteur (5), et une couche métallique de liaison de collecteur (6) est disposée au niveau de la position située d'un côté, à l'opposé du substrat (1), de la couche de collecteur (2) et à l'extérieur de la couche de dispositif (3). Selon le transistor, lorsque le transistor est électrifié, les électrons passent à travers la couche métallique de liaison d'émetteur (5), la couche de dispositif (3), la couche de collecteur (2) et la couche métallique de liaison de collecteur (6) en séquence pour réaliser une conduction de courant électrique, de telle sorte qu'un trajet de passage d'un courant électrique ne passe pas à travers le substrat (1), un substrat épais (1) peut être utilisé dans le transistor pour porter une couche de dispositif ultramince (3), et un processus d'amincissement ultramince et les étapes complexes associées ne sont pas nécessaires, ce qui permet de réduire le coût de fabrication et la difficulté de fabrication.
(ZH)
一种绝缘栅双极型晶体管及其制备方法,该晶体管中包括衬底(1),衬底(1)上设有集电极层(2)和器件层(3),器件层(3)在衬底(1)上的投影包括至少两个相对的侧边与集电极层(2)在衬底(1)上投影的边缘具有设定距离,器件层(3)外表面包覆有介质层(4),介质层(4)背离器件层(3)一侧形成有发射极键合金属层(5),集电极层(2)背离衬底(1)一侧位于器件层(3)以外区域内设有集电极键合金属层(6)。上述晶体管中,当对晶体管通电时,电子依次经过发射极键合金属层(5)、器件层(3)、集电极层(2)、集电极键合金属层(6),实现电流导通,从而电流的通过路径不经过衬底(1),使得晶体管中可以采用较厚的衬底(1)来承载超薄器件层(3),不需要采用超薄的减薄工艺和相关的复杂步骤,降低了制造成本以及制造难度。
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