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1. WO2020114053 - ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICE

Publication Number WO/2020/114053
Publication Date 11.06.2020
International Application No. PCT/CN2019/108660
International Filing Date 27.09.2019
IPC
H01L 27/12 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/77 2017.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
CPC
H01L 27/1248
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12the substrate being other than a semiconductor body, e.g. an insulating body
1214comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
1248with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
H01L 27/1259
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12the substrate being other than a semiconductor body, e.g. an insulating body
1214comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
1259Multistep manufacturing methods
Applicants
  • 京东方科技集团股份有限公司 BOE TECHNOLOGY GROUP CO., LTD. [CN]/[CN]
  • 成都京东方光电科技有限公司 CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN]/[CN]
Inventors
  • 曾超 ZENG, Chao
  • 黄炜赟 HUANG, Weiyun
  • 黄耀 HUANG, Yao
  • 高永益 KO, Youngyik
Agents
  • 中科专利商标代理有限责任公司 CHINA SCIENCE PATENT & TRADEMARK AGENT LTD.
Priority Data
201811486997.006.12.2018CN
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICE
(FR) SUBSTRAT MATRICIEL ET SON PROCÉDÉ DE FABRICATION, ET DISPOSITIF D'AFFICHAGE
(ZH) 阵列基板及其制造方法、显示装置
Abstract
(EN)
An array substrate, comprising a base substrate (40) and a display region (10) and a fan-out region (20) which are disposed on the base substrate. A signal line is disposed in the display region (10), the fan-out region (20) comprises a first fan-out line layer, a second fan-out line layer, and one or more spacing layers (55) between the first fan-out line layer and the second fan-out line layer, a first fan-out line (41a) is disposed in the first fan-out line layer, a second fan-out line (42a) is disposed in the second fan-out line layer, the signal line is connected to the first fan-out line (41a) or the second fan-out line (42a), and the spacing layers (55) are made of an insulating material, wherein the orthographic projection of the first fan-out line (41a) on the base substrate (40) and the orthographic projection of the second fan-out line (42a) on the base substrate (40) at least partially overlap. Further provided are a method for manufacturing the array substrate, and a display device.
(FR)
L'invention concerne un substrat matriciel, comprenant un substrat de base (40) et une région d'affichage (10) et une région de sortance (20) qui sont disposées sur le substrat de base. Une ligne de signal est disposée dans la région d'affichage (10), la région de sortance (20) comprend une première couche de ligne de sortance, une seconde couche de ligne de sortance et une ou plusieurs couches d'espacement (55) entre la première couche de ligne de sortance et la seconde couche de ligne de sortance, une première ligne de sortance (41a) est disposée dans la première couche de ligne de sortance, une seconde ligne de sortance (42a) est disposée dans la seconde couche de ligne de sortance, la ligne de signal est connectée à la première ligne de sortance (41a) ou à la seconde ligne de sortance (42a), et les couches d'espacement (55) sont constituées d'un matériau isolant, la projection orthographique de la première ligne de sortance (41a) sur le substrat de base (40) et la projection orthographique de la seconde ligne de sortance (42a) sur le substrat de base (40) se chevauchant au moins partiellement. L'invention concerne également un procédé de fabrication du substrat matriciel, et un dispositif d'affichage.
(ZH)
一种阵列基板,包括:衬底基板(40);以及设置在衬底基板上的显示区域(10)和扇出区域(20),在所述显示区域(10)中设置有信号线,所述扇出区域(20)包括第一扇出线层、第二扇出线层和在所述第一扇出线层与所述第二扇出线层之间的一个或更多个间隔层(55),在所述第一扇出线层中设置有第一扇出线(41a),在所述第二扇出线层中设置有第二扇出线(42a),所述信号线与所述第一扇出线(41a)或第二扇出线(42a)连接,所述间隔层(55)采用绝缘材料制作;其中,所述第一扇出线(41a)在衬底基板(40)上的正投影与所述第二扇出线(42a)在衬底基板(40)上的正投影至少存在部分重叠。还提供了一种阵列基板的制造方法和显示装置。
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