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1. WO2020113683 - TIMING CONTROL CHIP, DISPLAY DRIVING ASSEMBLY, AND DISPLAY APPARATUS

Publication Number WO/2020/113683
Publication Date 11.06.2020
International Application No. PCT/CN2018/121916
International Filing Date 19.12.2018
IPC
G09G 3/20 2006.01
GPHYSICS
09EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
CPC
G09G 3/20
GPHYSICS
09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix ; no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Applicants
  • 惠科股份有限公司 HKC CORPORATION LIMITED [CN]/[CN]
Inventors
  • 王明良 WANG, Mingliang
Agents
  • 深圳市世纪恒程知识产权代理事务所 CENFO INTELLECTUAL PROPERTY AGENCY
Priority Data
201811484655.505.12.2018CN
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) TIMING CONTROL CHIP, DISPLAY DRIVING ASSEMBLY, AND DISPLAY APPARATUS
(FR) PUCE DE COMMANDE DE SYNCHRONISATION, ENSEMBLE DE COMMANDE D'AFFICHAGE ET APPAREIL D’AFFICHAGE
(ZH) 时序控制芯片、显示驱动组件和显示装置
Abstract
(EN)
A timing control chip (110), a display driving assembly (100), and a display apparatus; the timing control chip (110) comprises at least two groups of mutually independent spread spectrum circuits (111, 112); the spread spectrum circuits (111, 112) are configured to convert initial clock signals (CLK) into spread spectrum clock signals (CLK1, CLK2) such that after conversion, the sum of the signal strengths of all of the clock signals (CLK1, CLK2) in the timing control chip (110) on any frequency is less than or equal to a corresponding preset strength threshold.
(FR)
La présente invention concerne une puce de commande de synchronisation (110), un ensemble de commande d'affichage (100) et un appareil d'affichage ; la puce de commande de synchronisation (110) comprend au moins deux groupes de circuits à spectre étalé mutuellement indépendants (111, 112) ; les circuits à spectre étalé (111, 112) sont configurés pour convertir des signaux d'horloge initiaux (CLK) en signaux d'horloge à spectre étalé (CLK1, CLK2) de telle sorte que, après conversion, la somme des intensités de signal de tous les signaux d'horloge (CLK1, CLK2) dans la puce de commande de synchronisation (110) sur n'importe quelle fréquence est inférieure ou égale à un seuil d'intensité préréglé correspondant.
(ZH)
一种时序控制芯片(110)、显示驱动组件(100)和显示装置,其中,时序控制芯片(110)包括至少两组相互独立的展频电路(111,112),展频电路(111,112)设置为将初始时钟信号(CLK)转换为展频时钟信号(CLK1,CLK2),以使转换后时序控制芯片(110)中所有时钟信号(CLK1,CLK2)在任一频率上的信号强度之和小于或等于对应的预设强度阈值。
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