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1. WO2020113590 - THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF

Publication Number WO/2020/113590
Publication Date 11.06.2020
International Application No. PCT/CN2018/119933
International Filing Date 07.12.2018
IPC
H01L 27/115 2017.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
CPC
H01L 21/76224
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
76Making of isolation regions between components
762Dielectric regions ; , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
76224using trench refilling with dielectric materials
H01L 21/76802
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76802by forming openings in dielectrics
H01L 21/76877
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76838characterised by the formation and the after-treatment of the conductors
76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
H01L 21/76898
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76898formed through a semiconductor substrate
H01L 23/481
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements
481Internal lead connections, e.g. via connections, feedthrough structures
H01L 23/5226
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
5226Via connections in a multilevel interconnection structure
Applicants
  • YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN]/[CN]
Inventors
  • XIAO, Li Hong
  • HUO, Zongliang
Agents
  • NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.
Priority Data
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF
(FR) DISPOSITIFS DE MÉMOIRE TRIDIMENSIONNELLE ET LEURS PROCÉDÉS DE FABRICATION
Abstract
(EN)
A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming multiple hybrid shallow trench isolation structures in a substrate; forming an alternating dielectric stack on the substrate, the alternating dielectric stack including multiple dielectric layer pairs each comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming multiple channel structures in the alternating dielectric stack; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction to divide the multiple channel structures and to expose a row of hybrid shallow trench isolation structures; replacing the second dielectric layers in the alternating dielectric stack with multiple gate structures through the slit; forming a spacer wall to fill the slit; and forming multiple array common source contacts each in electric contact with a corresponding hybrid shallow trench isolation structure.
(FR)
La présente invention concerne un procédé de formation d'une structure de grille d'un dispositif de mémoire 3D. Le procédé consiste à : former de multiples structures d'isolation de tranchée peu profonde hybrides dans un substrat ; former un empilement diélectrique alterné sur le substrat, l'empilement diélectrique alterné comprenant de multiples paires de couches diélectriques comprenant chacune une première couche diélectrique et une seconde couche diélectrique différente de la première couche diélectrique ; former de multiples structures de canal dans l'empilement diélectrique alterné ; former une fente pénétrant verticalement à travers l'empilement diélectrique alterné et s'étendant dans une direction horizontale pour diviser les multiples structures de canal et pour exposer une rangée de structures d'isolation de tranchée peu profonde hybride ; remplacer les secondes couches diélectriques dans l'empilement diélectrique alterné avec de multiples structures de grille à travers la fente ; former une paroi d'espacement pour remplir la fente ; et former de multiples contacts de source commune de réseau chacun en contact électrique avec une structure d'isolation de tranchée peu profonde hybride correspondante.
Also published as
CN201880002790.3
Latest bibliographic data on file with the International Bureau