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1. WO2020112884 - DRAM DEVICE WITH MULTIPLE VOLTAGE DOMAINS

Publication Number WO/2020/112884
Publication Date 04.06.2020
International Application No. PCT/US2019/063419
International Filing Date 26.11.2019
IPC
G11C 7/06 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
06Sense amplifiers; Associated circuits
G11C 7/08 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
06Sense amplifiers; Associated circuits
08Control thereof
G11C 7/12 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 11/408 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
408Address circuits
G11C 11/4094 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write circuits
4094Bit-line management or control circuits
H01L 27/108 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
CPC
G11C 11/4074
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
4074Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 11/4085
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
408Address circuits
4085Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
G11C 11/4091
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write [R-W] circuits 
4091Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
G11C 11/4094
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write [R-W] circuits 
4094Bit-line management or control circuits
G11C 2207/002
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
2207Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
002Isolation gates, i.e. gates coupling bit lines to the sense amplifier
G11C 2207/005
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
2207Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
005Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
Applicants
  • RAMBUS INC. [US]/[US]
Inventors
  • VOGELSANG, Thomas
Agents
  • NEUDECK, Alexander, J.
Priority Data
62/773,76130.11.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) DRAM DEVICE WITH MULTIPLE VOLTAGE DOMAINS
(FR) DISPOSITIF DRAM À MULTIPLES DOMAINES DE TENSION
Abstract
(EN)
A dynamic memory array of a DRAM device is operated using a bitline voltage that is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage used to store/retrieve data on the bitlines of the DRAM array. This allows lower voltage swing (and thus lower power) digital logic to be used for a majority of the non-storage array logic on the DRAM device – thus reducing the power consumption of the non-storage array logic which, in turn, reduces the power consumption of the DRAM device as a whole.
(FR)
L'invention concerne un réseau de mémoire dynamique d'un dispositif DRAM qui fonctionne à l'aide d'une tension de ligne de bits qui est supérieure à la tension de fonctionnement (c'est-à-dire, la commutation) d'une majorité des circuits logiques numériques du dispositif DRAM. Les circuits logiques numériques fonctionnent à l'aide d'une tension d'alimentation qui est inférieure à la tension utilisée pour stocker/récupérer des données sur les lignes de bits du réseau DRAM. Ceci permet à une logique numérique d'oscillation de tension inférieure (et donc de puissance inférieure) d'être utilisée pour une majorité de la logique de réseau de non-stockage sur le dispositif DRAM, réduisant ainsi la consommation de puissance de la logique de réseau de non-stockage qui, à son tour, réduit la consommation de puissance du dispositif DRAM dans son ensemble.
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