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1. WO2020112576 - DUAL-PRECISION ANALOG MEMORY CELL AND ARRAY

Publication Number WO/2020/112576
Publication Date 04.06.2020
International Application No. PCT/US2019/062895
International Filing Date 24.11.2019
IPC
G11C 14/00 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
14Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
G06F 3/00 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
G11C 5/02 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by group G11C11/63
02Disposition of storage elements, e.g. in the form of a matrix array
G11C 11/00 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
G11C 13/00 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
13Digital stores characterised by the use of storage elements not covered by groups G11C11/, G11C23/, or G11C25/173
CPC
G06N 3/06
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
G06N 5/04
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
5Computer systems using knowledge-based models
04Inference methods or devices
G11C 11/223
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
22using ferroelectric elements
223using MOS with ferroelectric gate insulating film
G11C 11/2255
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
22using ferroelectric elements
225Auxiliary circuits
2253Address circuits or decoders
2255Bit-line or column circuits
G11C 11/2257
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
22using ferroelectric elements
225Auxiliary circuits
2253Address circuits or decoders
2257Word-line or row circuits
G11C 11/2273
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
22using ferroelectric elements
225Auxiliary circuits
2273Reading or sensing circuits or methods
Applicants
  • HEFEI RELIANCE MEMORY LIMITED [CN]/[US]
Inventors
  • LU, Zhichao
  • ZHAO, Liang
Agents
  • CHEN, Weiguo
Priority Data
62/773,99130.11.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) DUAL-PRECISION ANALOG MEMORY CELL AND ARRAY
(FR) CELLULE DE MÉMOIRE ANALOGIQUE À DOUBLE PRÉCISION ET RÉSEAU
Abstract
(EN)
Dual-precision analog memory cells and arrays are provided. In some embodiments, a memory cell, comprises a non-volatile memory element having an input terminal and at least one output terminal; and a volatile memory element having a plurality of input terminals and an output terminal, wherein the output terminal of the volatile memory element is coupled to the input terminal of the non-volatile memory element, and wherein the volatile memory element comprises: a first transistor coupled between a first supply and a common node, and a second transistor coupled between a second supply and the common node; wherein the common node is coupled to the output terminal of the volatile memory element; and wherein gates of the first and second transistors are coupled to respective ones of the plurality of input terminals of the volatile memory element.
(FR)
L'invention concerne des cellules de mémoire analogique à double précision et des réseaux. Dans certains modes de réalisation, une cellule de mémoire comprend un élément de mémoire non volatile comprenant une borne d'entrée et au moins une borne de sortie; et un élément de mémoire volatile comprenant une pluralité de bornes d'entrée et une borne de sortie, la borne de sortie de l'élément de mémoire volatile étant couplée à la borne d'entrée de l'élément de mémoire non volatile, et l'élément de mémoire volatile comprenant : un premier transistor couplé entre une première alimentation et un noeud commun, et un second transistor couplé entre une seconde alimentation et le noeud commun; le noeud commun étant couplé à la borne de sortie de l'élément de mémoire volatile; et les grilles des premier et second transistors étant couplées à des bornes respectives de la pluralité de bornes d'entrée de l'élément de mémoire volatile.
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