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1. WO2020112485 - SRAM-BASED PROCESS IN MEMORY SYSTEM

Publication Number WO/2020/112485
Publication Date 04.06.2020
International Application No. PCT/US2019/062585
International Filing Date 21.11.2019
IPC
G06F 7/38 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
G06F 7/44 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
40using contact-making devices, e.g. electromagnetic relay
44Multiplying; Dividing
G06F 7/523 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
52Multiplying; Dividing
523Multiplying only
G11C 15/04 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
15Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
04using semiconductor elements
G11C 7/12 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
CPC
G06F 17/13
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
17Digital computing or data processing equipment or methods, specially adapted for specific functions
10Complex mathematical operations
11for solving equations ; , e.g. nonlinear equations, general mathematical optimization problems
13Differential equations
G06F 2207/4802
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2207Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
38Indexing scheme relating to groups G06F7/38 - G06F7/575
48Indexing scheme relating to groups G06F7/48 - G06F7/575
4802Special implementations
G06F 2207/4824
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2207Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
38Indexing scheme relating to groups G06F7/38 - G06F7/575
48Indexing scheme relating to groups G06F7/48 - G06F7/575
4802Special implementations
4818Threshold devices
4824Neural networks
G06F 7/5443
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
544for evaluating functions by calculation
5443Sum of products
G06F 9/3001
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
30007to perform operations on data operands
3001Arithmetic instructions
G11C 11/412
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
41forming ; static; cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
412using field-effect transistors only
Applicants
  • THE REGENTS OF THE UNIVERSITY OF MICHIGAN [US]/[US]
Inventors
  • ZHANG, Zhengya
  • CHEN, Thomas
  • BOTIMER, Jacob, Christopher
  • SONG, Shiming
Agents
  • GASH, Eric, J.
Priority Data
16/204,15329.11.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SRAM-BASED PROCESS IN MEMORY SYSTEM
(FR) PROCÉDÉ À BASE DE SRAM DANS UN SYSTÈME DE MÉMOIRE
Abstract
(EN)
Many signal processing, machine learning and scientific computing applications require a large number of multiply-accumuiate (MAC) operations. This type of operation is demanding in both computation and memory. Process in memory has been proposed as a new technique that computes directly on a large array of data in place, to eliminate expensive data movement overhead. To enable parallel multi-bit MAC operations, both width- and level- modulating memory word Sines are applied. To improve performance and provide tolerance against process-voltage-temperature variations, a delay-locked loop is used to generate fine unit pulses for driving memory word lines and a dual-ramp Single-slope ADC is used to convert bit line outputs. The concept is prototyped in a 180nm CMOS test chip made of four 320x64 compute-SRAMs, each supporting 128x parallel 5bx5b MACs with 32 5b output ADCs and consuming 16.6 mW at 200MHz.
(FR)
La présente invention concerne de nombreuses applications de traitement de signaux, d'apprentissage automatique et de calcul scientifique nécessitant un grand nombre d'opérations de multiplication-accumulation (MAC). Ce type de fonctionnement est exigeant aussi bien pour le calcul que pour la mémoire. Le procédé en mémoire a été proposé en tant que nouvelle technique qui effectue directement les calculs sur un grand réseau de données mis en place pour éliminer un surdébit coûteux de mouvement de données. Pour permettre des opérations MAC multi-bits parallèles, on applique des sinus de mot mémoire de modulation de largeur et de niveau. Pour améliorer les performances et fournir une tolérance vis-à-vis des variations de température de tension de traitement, une boucle à retardement verrouillé est utilisée pour générer des impulsions d'unité fines pour commander des lignes de mots de mémoire et un ADC à double rampe et à une pente est utilisé pour convertir des sorties de ligne de bits. Le concept est prototypé dans une puce d'essai CMOS de 180 nm constituée de quatre SRAM de calcul de 320x64, chacune prenant en charge 128x MAC parallèles de 5 bx5b avec 32 ADC de sortie 5b et consommant 16,6 mW à 200 MHz.
Also published as
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