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1. WO2020112391 - FAILURE-TOLERANT ERROR CORRECTION LAYOUT FOR MEMORY SUB-SYSTEMS

Publication Number WO/2020/112391
Publication Date 04.06.2020
International Application No. PCT/US2019/061838
International Filing Date 15.11.2019
IPC
G06F 11/10 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 29/52 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
52Protection of memory contents; Detection of errors in memory contents
CPC
G06F 11/1076
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1076Parity data used in redundant arrays of independent storages, e.g. in RAID systems
H03M 13/098
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
09Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
098using single parity bit
H03M 13/152
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
13Linear codes
15Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
151using error location or error correction polynomials
152Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/1525
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
13Linear codes
15Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
151using error location or error correction polynomials
1525Determination and particular use of error location polynomials
H03M 13/27
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
27using interleaving techniques
H03M 13/2906
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
29combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
2906using block codes
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • WU, Wei
  • SHEN, Zhenlei
  • CHEN, Zhengang
Agents
  • PORTNOVA, Marina
  • SHEKHER, Rahul
  • KRUEGER, Paul M.
  • DATTA, Madhumita
Priority Data
16/205,07529.11.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) FAILURE-TOLERANT ERROR CORRECTION LAYOUT FOR MEMORY SUB-SYSTEMS
(FR) AGENCEMENT DE CORRECTION D'ERREUR TOLÉRANT AUX DÉFAILLANCES POUR SOUS-SYSTÈMES DE MÉMOIRE
Abstract
(EN)
Codewords of an error correcting code can be received. The codewords can be separated into multiple segments. The segments of the codewords can be distributed in an error correcting layout across a plurality of dies where at least a portion of the error correcting layout constitutes a Latin Square (LS) layout.
(FR)
Selon l'invention, des mots de code d'un code de correction d'erreur peuvent être reçus. Les mots de code peuvent être séparés en de multiples segments. Les segments des mots de code peuvent être distribués selon un agencement de correction d'erreur sur une pluralité de puces où au moins une partie de l'agencement de correction d'erreur constitue un agencement en carré latin (LS).
Also published as
Latest bibliographic data on file with the International Bureau