Processing

Please wait...

Settings

Settings

Goto Application

1. WO2020112320 - LAST-LEVEL COLLECTIVE HARDWARE PREFETCHING

Publication Number WO/2020/112320
Publication Date 04.06.2020
International Application No. PCT/US2019/060127
International Filing Date 06.11.2019
IPC
G06F 12/0862 2016.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0862with prefetch
CPC
G06F 12/0862
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0862with prefetch
G06F 2212/6026
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
60Details of cache memory
6026Prefetching based on access pattern detection, e.g. stride based prefetch
Applicants
  • THE REGENTS OF THE UNIVERSITY OF CALIFORNIA [US]/[US]
Inventors
  • MICHELOGIANNAKIS, Georgios
  • SHALF, John
Agents
  • OVANEZIAN, Daniel E.
  • GENCARELLA, Michael L.
  • REPLOGLE, Eric S.
  • JACOBS, JR., William D.
  • WOLFSBERGER, Jonathan
  • ADESESH, Abhijit P.
Priority Data
62/772,98729.11.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) LAST-LEVEL COLLECTIVE HARDWARE PREFETCHING
(FR) LECTURE ANTICIPÉE DE MATÉRIEL COLLECTIF DE DERNIER NIVEAU
Abstract
(EN)
A last-level collective hardware prefetcher (LLCHP) is described. The LLCHP is to detect a first off-chip memory access request by a first processor core of a plurality of processor cores. The LLCHP is further to determine, based on the first off-chip memory access request, that first data associated with the first off-chip memory access request is associated with second data of a second processor core of the plurality of processor cores. The LLCHP is further to prefetch the first data and the second data based on the determination.
(FR)
L'invention concerne un dispositif de lecture anticipée de matériel collectif de dernier niveau (LLCHP). Le LLCHP sert à détecter une première demande d'accès mémoire hors puce au moyen d'un premier cœur de processeur d'une pluralité de cœurs de processeur. Le LLCHP sert en outre à déterminer, sur la base de la première demande d'accès mémoire hors puce, que les premières données associées à la première demande d'accès mémoire hors puce sont associées à des secondes données d'un second cœur de processeur de la pluralité de cœurs de processeur. Le LLCHP sert en outre à la lecture anticipée des premières données et des secondes données sur la base de la détermination.
Latest bibliographic data on file with the International Bureau