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1. WO2020112296 - VERTICAL DECODER

Publication Number WO/2020/112296
Publication Date 04.06.2020
International Application No. PCT/US2019/059037
International Filing Date 31.10.2019
IPC
H01L 27/108 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
H01L 27/06 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
06including a plurality of individual components in a non-repetitive configuration
CPC
G11C 5/02
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
02Disposition of storage elements, e.g. in the form of a matrix array
G11C 5/063
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
06Arrangements for interconnecting storage elements electrically, e.g. by wiring
063Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
G11C 8/10
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
8Arrangements for selecting an address in a digital store
10Decoders
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • REDAELLI, Andrea
  • PELLIZZER, Fabio
Agents
  • HARRIS, Philip
Priority Data
16/206,00630.11.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) VERTICAL DECODER
(FR) DÉCODEUR VERTICAL
Abstract
(EN)
Methods, systems, and devices for a decoder are described. The memory device may include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate. The decoder may be configured to apply a voltage to an access line of the array of memory cells as part of an access operation. The decoder may include a first conductive line configured to carry the voltage applied to the access line of the array of memory cells. In some cases, the decoder may include a doped material extending between the first conductive line and the access line of the array of memory cells in a first direction (e.g., away from a surface of the substrate) and the doped material may be configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells.
(FR)
L’invention concerne des procédés, des systèmes et des dispositifs pour un décodeur. Le dispositif de mémoire peut comprendre un substrat, un réseau de cellules de mémoire couplées au substrat, ainsi qu'un décodeur couplé au substrat. Le décodeur peut être configuré pour appliquer une tension sur une ligne d'accès du réseau de cellules de mémoire dans le cadre d'une opération d'accès. Le décodeur peut comprendre une première ligne conductrice configurée pour transporter la tension appliquée sur la ligne d'accès du réseau de cellules de mémoire. Dans certains cas, le décodeur peut comprendre un matériau dopé s'étendant entre la première ligne conductrice et la ligne d'accès du réseau de cellules de mémoire dans une première direction (par exemple, à distance d'une surface du substrat) et le matériau dopé peut être configuré pour coupler de façon sélective la première ligne conductrice du décodeur à la ligne d'accès du réseau de cellules de mémoire.
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