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1. WO2020112285 - ERROR CORRECTION BIT FLIPPING SCHEME

Publication Number WO/2020/112285
Publication Date 04.06.2020
International Application No. PCT/US2019/058141
International Filing Date 25.10.2019
IPC
G11C 29/52 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
52Protection of memory contents; Detection of errors in memory contents
G06F 11/10 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
H03M 13/11 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
CPC
G06F 11/1068
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1008in individual solid state devices
1068in sector programmable memories, e.g. flash disk
G11C 2029/0411
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
0411Online error correction
G11C 29/52
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
52Protection of memory contents; Detection of errors in memory contents
H03M 13/05
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
H03M 13/1108
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
1105Decoding
1108Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • KWAK, Jongtae
Agents
  • HARRIS, Philip
Priority Data
16/199,77326.11.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) ERROR CORRECTION BIT FLIPPING SCHEME
(FR) SCHÉMA DE BASCULEMENT DE BITS DE CORRECTION D'ERREUR
Abstract
(EN)
Methods, systems, and devices for operating a memory device are described. An error correction bit flipping scheme may include methods, systems, and devices for performing error correction of one or more bits (e.g., a flip bit) and for efficiently communicating error correction information. The data bits and the flip bit (e.g., an error corrected flip bit) may be directly transmitted (e.g., to a flip decision component). The flip bit may be transmitted to the flip decision component over a dedicated and/or unidirectional line that is different from one or more other lines that carry data bits (e.g., to the flip decision component).
(FR)
L'invention concerne des procédés, des systèmes et des dispositifs permettant de faire fonctionner un dispositif mémoire. Un schéma de basculement de bits de correction d'erreur peut comprendre des procédés, des systèmes et des dispositifs pour effectuer une correction d'erreur d'un ou de plusieurs bits (par exemple, un bit de basculement) et pour communiquer efficacement des informations de correction d'erreur. Les bits de données et le bit de basculement (par exemple, un bit de basculement ayant fait l'objet d'une correction d'erreur) peuvent être transmis directement (par exemple, à un composant de décision de basculement). Le bit de basculement peut être transmis au composant de décision de basculement sur une ligne dédiée et/ou unidirectionnelle qui est différente d'une ou de plusieurs autres lignes qui portent des bits de données (par exemple, au composant de décision de basculement).
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