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1. WO2020112259 - FRACTIONAL FREQUENCY SYNTHESIS BY SIGMA-DELTA MODULATING FREQUENCY OF A REFERENCE CLOCK

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[ EN ]

CLAIMS

What is claimed is:

1. A circuit (30) comprising:

a programmable frequency divider (14) which receives a high-speed clock (12 ),fm, as an input and which provides a modulated reference clock (20) as an output;

a Sigma-Delta modulator (16) which receives a Frequency Control Word (FCW) (18) and which is connected to the programmable frequency divider (14) to receive the modulated reference clock (20) as a sample clock and to control an average frequency of the modulated reference clock (20); and

an integer-N Phase Lock Loop (PLL) (22) which receives the modulated reference clock (20) and outputs a clock output.

2. The circuit (30) as claimed in claim 1, wherein the modulated reference clock (20)

fin

average frequency is equal to j +FC^ ar|d wherein the clock output frequency is equal to

f. _ L_

J in I+FCW

3. The circuit (30) as claimed in claims 1-2, wherein the high-speed clock (12) is from a second PLL (36) associated with the circuit (30).

4. The circuit (30) as claimed in claim 3, wherein the second Phase Lock Loop (PLL) (36) is for a Digital-Analog Converter (DAC) sampling clock.

5. The circuit (30) as claimed in claims 1-4, wherein the circuit (30) further comprises an integer divisor (I) (26) that is connected to the programmable frequency divisor (14), and provides a Numerically Controlled Oscillator (NCO) function based on selected values for the FCW (18), the integer divisor (26), and the integer-N PLL (22), and wherein the circuit (30) drives a Serializer/Deserializer (SerDes).

6. The circuit as claimed in claim 1 , wherein the FCW (18) defines a numerator value for the programmable frequency divider (14), and a denominator value for the programmable

frequency divider (14) is set by one of i) rail voltages for an analog Sigma-Delta modulator and ii) a number of accumulator bits for a digital Sigma-Delta modulator.

7. The circuit as claimed in claim 1, wherein the circuit is disposed in an Application Specific Integrated Circuit (ASIC) on a Printed Circuit Board (PCB).

8. The circuit as claimed in claim 7, wherein the high-speed clock (12) is from a second PLL on the ASIC which receives an input reference clock from the PCB.

9. A method of operating a circuit (30) comprising:

receiving a high-speed clock ( 1
as an input to a programmable frequency divider

(14);

modulating the high-speed clock (12) with a Sigma-Delta modulator (16) which is connected to the programmable frequency divider (14) to control an average frequency of an output of programmable frequency divider (14);

controlling the Sigma-Delta modulator (16) with a Frequency Control Word (FCW) (18) and an integer divisor, each of the FCW (18) and the integer divisor is connected to the programmable frequency divider (14);

providing an output of the programmable frequency divider (14) as a modulated reference clock (20), wherein the modulated reference clock (20) is connected to the Sigma-Delta modulator (16) as a sample clock; and

receiving the modulated reference clock (20) at an integer-N Phase Lock Loop (PLL) (22) and outputting a clock output.

10. The method as claimed in claim 9, wherein the modulated reference clock average (20)

frequency is equal to

ar|d wherein the clock output frequency is equal to fin I+FCW·

11. The method as claimed in claims 9-10, wherein the high-speed clock is from a second Phase Lock Loop (PLL) (36) associated with the circuit (30).

12. The method as claimed in claims 9-11, wherein the circuit provides a Numerically Controlled Oscillator (NCO) function based on selected values for the FCW (18), the integer divisor, and the integer-N PLLC (22), and wherein the circuit (30) drives a Serializer/Deserializer (SerDes).

13. The method as claimed in claims 9-12, wherein the F CW (18) defines a numerator value for the programmable frequency divider (14) and a denominator value for the programmable frequency divider (18) is set by one of i) rail voltages for an analog Sigma-Delta modulator and ii) a number of accumulator bits for a digital Sigma-Delta modulator.

14. The method as claimed in claims 9-13, wherein the circuit is disposed in an Application Specific Integrated Circuit (ASIC) on a Printed Circuit Board (PCB).

15. The method as claimed in claim 15, wherein the high-speed clock (12) is from a second PLL (36) on the ASIC which receives an input reference clock from the PCB.