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1. WO2020112259 - FRACTIONAL FREQUENCY SYNTHESIS BY SIGMA-DELTA MODULATING FREQUENCY OF A REFERENCE CLOCK

Publication Number WO/2020/112259
Publication Date 04.06.2020
International Application No. PCT/US2019/056029
International Filing Date 14.10.2019
IPC
H03L 7/18 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
18using a frequency divider or counter in the loop
H03L 7/22 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
22using more than one loop
CPC
H03L 7/18
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
18using a frequency divider or counter in the loop
H03L 7/1976
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
18using a frequency divider or counter in the loop
197a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
1974for fractional frequency division
1976using a phase accumulator for controlling the counter or frequency divider
H03L 7/22
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
22using more than one loop
Applicants
  • CIENA CORPORATION [US]/[US]
Inventors
  • AOUINI, Sadok
  • MIKKELSEN, Matthew
  • BEN-HAMIDA, Naim
  • PARVIZI, Mahdi
  • WEN, Tingjun
  • PLETT, Calvin
Agents
  • BARATTA, Lawrence, A., Jr.
Priority Data
16/205,30830.11.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) FRACTIONAL FREQUENCY SYNTHESIS BY SIGMA-DELTA MODULATING FREQUENCY OF A REFERENCE CLOCK
(FR) SYNTHÈSE DE FRÉQUENCE FRACTIONNAIRE PAR LA FRÉQUENCE DE MODULATION SIGMA-DELTA D'UNE HORLOGE DE RÉFÉRENCE
Abstract
(EN)
A circuit (30) includes a programmable frequency divider (14) which receives a high-speed clock (12), ƒin, as an input and which provides a modulated reference clock (20) as an output; a Sigma-Delta modulator (16) which receives a Frequency Control Word (FCW) (18) and which is connected to the programmable frequency divider (14) to receive the modulated reference clock (20) as a sample clock and to control an average frequency of the modulated reference clock (20); and an integer-N Phase Lock Loop (PLL) (22) which receives the modulated reference clock (20) and outputs a clock output..
(FR)
Un circuit (30) comprend un diviseur de fréquence programmable (14) qui reçoit une horloge à grande vitesse (12), ƒin, en tant qu'entrée et qui fournit une horloge de référence modulée (20) en tant que sortie ; un modulateur Sigma-Delta (16) qui reçoit un mot de commande de fréquence (FCW) (18) et qui est connecté au diviseur de fréquence programmable (14) pour recevoir l'horloge de référence modulée (20) en tant qu'horloge d'échantillon et pour commander une fréquence moyenne de l'horloge de référence modulée (20) ; et une boucle à verrouillage de phase (PLL) à nombre entier N (22) qui reçoit l'horloge de référence modulée (20) et délivre en sortie une sortie d'horloge.
Also published as
Latest bibliographic data on file with the International Bureau