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1. WO2020112255 - CONCEPT FOR A BUFFERED FLIPPED VOLTAGE FOLLOWER AND FOR A LOW DROPOUT VOLTAGE REGULATOR

Publication Number WO/2020/112255
Publication Date 04.06.2020
International Application No. PCT/US2019/055489
International Filing Date 10.10.2019
IPC
H03F 3/50 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
FAMPLIFIERS
3Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
50Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower
H03F 3/45 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
FAMPLIFIERS
3Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
45Differential amplifiers
CPC
G05F 1/575
GPHYSICS
05CONTROLLING; REGULATING
FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
1Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
10Regulating voltage or current
46wherein the variable actually regulated by the final control device is dc
56using semiconductor devices in series with the load as final control devices
575characterised by the feedback circuit
G05F 1/618
GPHYSICS
05CONTROLLING; REGULATING
FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
1Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
10Regulating voltage or current
46wherein the variable actually regulated by the final control device is dc
618using semiconductor devices in series and in parallel with the load as final control devices
H03F 3/45183
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
FAMPLIFIERS
3Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
45Differential amplifiers
45071with semiconductor devices only
45076characterised by the way of implementation of the active amplifying circuit in the differential amplifier
45179using MOSFET transistors as the active amplifying circuit
45183Long tailed pairs
H03F 3/505
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
FAMPLIFIERS
3Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
50Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower
505with field-effect devices
Applicants
  • INTEL CORPORATION [US]/[US]
Inventors
  • GRUBER, Daniel
  • KALCHER, Michael
Agents
  • O'LEARY, Kieran
Priority Data
10 2018 129 910.927.11.2018DE
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) CONCEPT FOR A BUFFERED FLIPPED VOLTAGE FOLLOWER AND FOR A LOW DROPOUT VOLTAGE REGULATOR
(FR) CONCEPT POUR UN SUIVEUR DE TENSION BASCULÉ TAMPONNÉ ET POUR UN RÉGULATEUR DE TENSION À FAIBLE CHUTE DE TENSION
Abstract
(EN)
Examples relate to a buffered flipped voltage follower circuit arrangement, low dropout voltage regulators, a capacitive digital-to-analog converter, a transceiver for wireless communication, a mobile communication device, a base station transceiver, and to a method for forming a buffered flipped voltage follower circuit arrangement. The buffered flipped voltage follower circuit arrangement comprises a first transistor (Mp) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a second transistor (Mc) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a buffer circuit comprising an input terminal and an output terminal. The buffered flipped voltage follower circuit arrangement a feed-forward compensation circuit (— gmf ) comprising an input terminal and an output terminal. The first terminal of the first transistor (Mp) is coupled to a supply voltage of the flipped voltage follower circuit. The second terminal of the first transistor (Mp) is coupled with the first terminal of the second transistor (Mc) and with an output voltage terminal of the buffered flipped voltage follower circuit arrangement. The second terminal of the second transistor (Mc) is coupled with the input terminal of the buffer circuit and with the output terminal of the feed-forward compensation circuit (— gmf )· The gate terminal of the first transistor (MP) is coupled with the output terminal of the buffer circuit and with the input terminal of the feed-forward compensation circuit (— gmf
(FR)
Des exemples de la présente invention concernent un agencement de circuit suiveur de tension basculé tamponné, des régulateurs de tension à faible chute de tension, un convertisseur numérique-analogique capacitif, un émetteur-récepteur pour une communication sans fil, un dispositif de communication mobile, un émetteur-récepteur de station de base, et un procédé de formation d'un agencement de circuit suiveur de tension basculé tamponné,. L'agencement de circuit suiveur de tension basculé tamponné, comprend un premier transistor (M p ) comprenant une première borne, une seconde borne et une borne de grille. L'agencement de circuit suiveur de tension basculé tamponné comprend un second transistor (M c )) comprenant une première borne, une seconde borne et une borne de grille. L'agencement de circuit suiveur de tension basculé tamponné comprend un circuit tampon comprenant une borne d'entrée et une borne de sortie. Le circuit suiveur de tension basculé tamponné comprend un circuit de compensation d'action directe (— g mf ) ) comprenant une borne d'entrée et une borne de sortie. La première borne du premier transistor (M p ) est couplée à une tension d'alimentation du circuit suiveur de tension basculé. La seconde borne du premier transistor (M p ) est couplée à la première borne du second transistor (M c ) et à une borne de tension de sortie de l'agencement de circuit suiveur de tension basculé tamponné. La seconde borne du second transistor (Mc) est couplée à la borne d'entrée du circuit tampon et à la borne de sortie du circuit de compensation d'action directe (— g mf ). La borne de grille du premier transistor (MP) est couplée à la borne de sortie du circuit tampon et à la borne d'entrée du circuit de compensation d'action directe (— g mf ).
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Latest bibliographic data on file with the International Bureau