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1. WO2020112209 - METHODS AND SYSTEMS FOR EFFICIENT ENCODING AND DECODING COMMUNICATIONS

Publication Number WO/2020/112209
Publication Date 04.06.2020
International Application No. PCT/US2019/050864
International Filing Date 12.09.2019
IPC
H04L 29/06 2006.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
29Arrangements, apparatus, circuits or systems, not covered by a single one of groups H04L1/-H04L27/136
02Communication control; Communication processing
06characterised by a protocol
H04L 9/00 2006.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
9Arrangements for secret or secure communication
CPC
G06F 3/0623
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers, ; e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0602specifically adapted to achieve a particular effect
062Securing storage systems
0623in relation to content
G06F 3/0632
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers, ; e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0628making use of a particular technique
0629Configuration or reconfiguration of storage systems
0632by initialisation or re-initialisation of storage systems
G06F 3/067
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers, ; e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0668adopting a particular infrastructure
067Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
H03M 13/09
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
09Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
H04L 9/0618
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
9Cryptographic mechanisms or cryptographic; arrangements for secret or secure communication
06the encryption apparatus using shift registers or memories for block-wise ; or stream; coding, e.g. DES systems ; or RC4; Hash functions; Pseudorandom sequence generators
0618Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
H04L 9/0631
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
9Cryptographic mechanisms or cryptographic; arrangements for secret or secure communication
06the encryption apparatus using shift registers or memories for block-wise ; or stream; coding, e.g. DES systems ; or RC4; Hash functions; Pseudorandom sequence generators
0618Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
0631Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
Applicants
  • SEAPORT, INC. [US]/[US]
Inventors
  • BAYLEY, Gwain
  • VAN DUYNE, William F.
  • SPAZANTE, William
Agents
  • ABUMERI, Mark M.
Priority Data
62/731,63714.09.2018US
62/731,71414.09.2018US
62/811,24927.02.2019US
62/845,75709.05.2019US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) METHODS AND SYSTEMS FOR EFFICIENT ENCODING AND DECODING COMMUNICATIONS
(FR) PROCÉDÉS ET SYSTÈMES POUR CODAGE ET DÉCODAGE EFFICACE DE COMMUNICATIONS
Abstract
(EN)
In some aspects, an apparatus for encoding a stream of data for transmission to a receiver device comprises a memory device and a hardware processor. The memory device is a memory device configured to store at least one parameter associated with at least one cryptographic protocol, the at least one parameter identifying one or more cipher directives from a plurality of cipher directives including an exclusive-OR (XOR) function and a table lookup function. The hardware processor is configured to generate, for transmission to the receiver device, a frame comprising a first field identifying a custom or non-custom cryptographic scheme and a second field identifying a first cipher directive of the plurality of cipher directives.
(FR)
Selon certains aspects, l'invention concerne un appareil pour coder un flux de données pour une transmission vers un dispositif récepteur comportant un dispositif de mémoire et un processeur matériel. Le dispositif de mémoire est un dispositif de mémoire configuré pour stocker au moins un paramètre associé à au moins un protocole cryptographique, ledit au moins un paramètre identifiant au moins une directive de chiffrement parmi une pluralité de directives de chiffrement comprenant une fonction OU exclusif (XOR) et une fonction de recherche. Le processeur matériel est configuré pour générer, en vue d'une transmission vers le dispositif récepteur, une trame comprenant un premier champ identifiant un schéma cryptographique personnalisé ou non personnalisé et un second champ identifiant une première directive de chiffrement parmi la pluralité de directives de chiffrement.
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