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1. WO2020112173 - REDUCTION OF ZQ CALIBRATION TIME

Publication Number WO/2020/112173
Publication Date 04.06.2020
International Application No. PCT/US2019/041002
International Filing Date 09.07.2019
IPC
G11C 29/50 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
04Detection or location of defective memory elements
50Marginal testing, e.g. race, voltage or current testing
G11C 7/10 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 11/4093 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write circuits
4093Input/output data interface arrangements, e.g. data buffers
CPC
G06F 3/0604
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers, ; e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0602specifically adapted to achieve a particular effect
0604Improving or facilitating administration, e.g. storage management
G06F 3/0632
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers, ; e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0628making use of a particular technique
0629Configuration or reconfiguration of storage systems
0632by initialisation or re-initialisation of storage systems
G06F 3/0673
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers, ; e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0668adopting a particular infrastructure
0671In-line storage system
0673Single storage device
G11C 2207/2254
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
2207Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
22Control and timing of internal memory operations
2254Calibration
G11C 7/1048
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1048Data bus control circuits, e.g. precharging, presetting, equalising
G11C 7/1057
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
1057Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • SATOH, Yasuo
  • HE, Yuan
Agents
  • PARKER, Paul, T.
  • ALLBEE, Dannon
  • DUNHAM, Nicole, S.
  • SAEM, Han, (sam) Hong
  • ARNETT, Stephen, E.
Priority Data
16/205,45030.11.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) REDUCTION OF ZQ CALIBRATION TIME
(FR) RÉDUCTION DU TEMPS D'ÉTALONNAGE ZQ
Abstract
(EN)
A memory system includes an external calibration device that has a predetermined impedance and a first memory device with a first pad for selective connection to the external calibration device. The first memory device also includes an internal calibration device having an impedance that is programmable and a second pad connected to the internal calibration device. The system further includes a second memory device having a third pad for selective connection to the second pad of the first memory device. A processing device is operatively coupled to the first memory device and the second memory device. The processing device programs the impedance of the internal calibration device of the first memory device based on the external calibration device, and programs an impedance of a termination component in the second memory device based on the impedance of the internal calibration device of the first memory device.
(FR)
L'invention concerne un système de mémoire qui comprend un dispositif d'étalonnage externe qui comprend une impédance prédéterminée et un premier dispositif de mémoire avec un premier tampon pour une connexion sélective au dispositif d'étalonnage externe. Le premier dispositif de mémoire comprend également un dispositif d'étalonnage interne comprenant une impédance qui est programmable et un second tampon connecté au dispositif d'étalonnage interne. Le système comprend en outre un second dispositif de mémoire comprenant un troisième tampon pour une connexion sélective au second tampon du premier dispositif de mémoire. Un dispositif de traitement est fonctionnellement couplé au premier dispositif de mémoire et au second dispositif de mémoire. Le dispositif de traitement programme l'impédance du dispositif d'étalonnage interne du premier dispositif de mémoire sur la base du dispositif d'étalonnage externe, et programme une impédance d'un composant de terminaison dans le second dispositif de mémoire sur la base de l'impédance du dispositif d'étalonnage interne du premier dispositif de mémoire.
Also published as
Latest bibliographic data on file with the International Bureau