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1. WO2020112169 - AGGREGATING COMMANDS IN A STREAM BASED ON CACHE LINE ADDRESSES

Publication Number WO/2020/112169
Publication Date 04.06.2020
International Application No. PCT/US2019/037657
International Filing Date 18.06.2019
IPC
G06F 3/06 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from, or digital output to, record carriers
G06F 12/0802 2016.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
CPC
G06F 12/0804
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0804with main memory updating
G06F 2212/1044
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
10Providing a specific technical effect
1041Resource optimization
1044Space efficiency improvement
G06F 2212/608
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
60Details of cache memory
608Details relating to cache mapping
G06F 3/0604
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers, ; e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0602specifically adapted to achieve a particular effect
0604Improving or facilitating administration, e.g. storage management
G06F 3/0659
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers, ; e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0628making use of a particular technique
0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
0659Command handling arrangements, e.g. command buffers, queues, command scheduling
G06F 3/0673
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers, ; e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0668adopting a particular infrastructure
0671In-line storage system
0673Single storage device
Applicants
  • ADVANCED MICRO DEVICES, INC. [US]/[US]
Inventors
  • BRENNAN, Christopher J.
Agents
  • SHEEHAN, Adam D.
Priority Data
16/205,09429.11.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) AGGREGATING COMMANDS IN A STREAM BASED ON CACHE LINE ADDRESSES
(FR) AGRÉGATION DE COMMANDES DANS UN FLUX EN FONCTION D'ADRESSES DE LIGNES DE MÉMOIRE CACHE
Abstract
(EN)
An operation combiner [240] receives a series of commands with read addresses, a modification operation, and write addresses. In some cases, the commands have serial dependencies that limit the rate at which they can be processed. The operation combiner compares the addresses for compatibility, transforms the operations to break serial dependencies, and combines multiple source commands into a smaller number of aggregate commands that can be executed much faster than the source commands. Some embodiments of the operation combiner receive a first command including one or more first read addresses and a first write address. The operation combiner compares the first read addresses and the first write address to one or more second read addresses and a second write address of a second command stored in a buffer. The operation combiner selectively combines the first and second commands to form an aggregate command based on the comparison.
(FR)
L'invention concerne un combinateur d'opérations (240) recevant une série de commandes à adresses de lecture, une opération de modification et des adresses d'écriture. Dans certains cas, les commandes ont des dépendances en série qui limitent la vitesse à laquelle elles peuvent être traitées. Le combinateur d'opérations compare la compatibilité des adresses, transforme les opérations pour rompre des dépendances en série et combine de multiples commandes de source en un nombre plus petit de commandes d'agrégat qui peuvent être exécutées bien plus rapidement que les commandes de source. Certains modes de réalisation du combineur d'opérations reçoivent une première commande comprenant une ou plusieurs premières adresses de lecture et une première adresse d'écriture. Le combineur d'opérations compare les premières adresses de lecture et la première adresse d'écriture à une ou à plusieurs secondes adresses de lecture et à une seconde adresse d'écriture d'une seconde commande stockée dans une mémoire tampon. Le combinateur d'opérations combine sélectivement les première et seconde commandes pour former une commande agrégée en fonction de la comparaison.
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