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1. WO2020110895 - COMMUNICATION DEVICE, INFORMATION PROCESSING SYSTEM, AND COMMUNICATION METHOD

Publication Number WO/2020/110895
Publication Date 04.06.2020
International Application No. PCT/JP2019/045601
International Filing Date 21.11.2019
IPC
G06F 13/12 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
10Program control for peripheral devices
12using hardware independent of the central processor, e.g. channel or peripheral processor
G06F 13/16 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
G06F 13/36 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
36for access to common bus or bus system
G06F 13/38 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
H04L 12/70 2013.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12Data switching networks
70Packet switching systems
G06F 12/06 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
06Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
CPC
G06F 12/06
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
G06F 13/12
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
10Program control for peripheral devices
12using hardware independent of the central processor, e.g. channel or peripheral processor
G06F 13/16
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
G06F 13/36
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
36for access to common bus or bus system
G06F 13/38
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
G06F 15/173
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general
16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
163Interprocessor communication
173using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
Applicants
  • 日本電気株式会社 NEC CORPORATION [JP]/[JP]
Inventors
  • 馬場 紀圭 BABA Kiyoshi
Agents
  • 下坂 直樹 SHIMOSAKA Naoki
Priority Data
2018-22457230.11.2018JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) COMMUNICATION DEVICE, INFORMATION PROCESSING SYSTEM, AND COMMUNICATION METHOD
(FR) DISPOSITIF DE COMMUNICATION, DISPOSITIF DE TRAITEMENT D'INFORMATIONS ET PROCÉDÉ DE COMMUNICATION
(JA) 通信装置、情報処理システム、および通信方法
Abstract
(EN)
A communication device mounted in each of a plurality of information processing devices connected to a fabric in order to enable a memory space to be shared by the plurality of information processing devices. The communication device is provided with: a serial interface for transmitting/receiving a first packet compliant with a Peripheral Component Interconnect Express (PCIe) standard; a requester unit for acquiring a first packet from the serial interface and converting the acquired first packet to a second packet transmitted/received via a fabric between a plurality of information processing devices sharing a memory space virtually extended using device identifiers specific to the information processing devices; a fabric communication unit for transmitting/receiving a second packet via the fabric; and a completer unit for acquiring a second packet from the fabric communication unit and generating a response packet to the request included in the acquired second packet.
(FR)
La présente invention concerne un dispositif de communication monté dans chaque dispositif d'une pluralité de dispositifs de traitement d’informations étant connecté à une matrice afin de permettre à un espace mémoire d'être partagé par la pluralité de dispositifs de traitement d’informations. Le dispositif de communication comprend : une interface série permettant de transmettre/recevoir un premier paquet conforme à une interconnexion expresse de composants périphériques (PCIe) standard ; une unité de demandeur permettant d'acquérir un premier paquet à partir de l'interface série et de convertir le premier paquet acquis en un second paquet transmis/reçu par l'intermédiaire d'une matrice entre une pluralité de dispositifs de traitement d’informations partageant un espace mémoire pour ainsi dire étendu à l'aide d'identifiants de dispositif spécifiques aux dispositifs de traitement d’informations ; une unité de communication de matrice permettant de transmettre/recevoir un second paquet par l'intermédiaire de la matrice ; et une unité d'achèvement permettant d'acquérir un second paquet à partir de l'unité de communication de matrice et de générer un paquet de réponse à la demande comprise dans le second paquet acquis.
(JA)
複数の情報処理装置がメモリ空間を共有することを可能とするために、ファブリックに接続された複数の情報処理装置のそれぞれに実装される通信装置であって、PCIe(Peripheral Component Interconnect Express)規格の第1パケットを送受信するシリアルインタフェースと、シリアルインタフェースから第1パケットを取得し、取得した第1パケットを、情報処理装置に固有の装置識別子を用いて仮想的に拡張されたメモリ空間を共有する複数の情報処理装置の間でファブリックを介して送受信される第2パケットに変換するリクエスタ部と、ファブリックを介して第2パケットを送受信するファブリック通信部と、ファブリック通信部から第2パケットを取得し、取得した第2パケットに含まれるリクエストに対する応答パケットを生成するコンプリータ部とを備える通信装置とする。
Also published as
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