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1. WO2020110285 - SEMICONDUCTOR DEVICE

Publication Number WO/2020/110285
Publication Date 04.06.2020
International Application No. PCT/JP2018/044153
International Filing Date 30.11.2018
IPC
H01L 29/78 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
CPC
H01L 29/78
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
76Unipolar devices ; , e.g. field effect transistors
772Field effect transistors
78with field effect produced by an insulated gate
Applicants
  • 三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP]/[JP]
Inventors
  • 川原 洸太朗 KAWAHARA Kotaro
  • 日野 史郎 HINO Shiro
Agents
  • 吉竹 英俊 YOSHITAKE Hidetoshi
  • 有田 貴弘 ARITA Takahiro
Priority Data
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置
Abstract
(EN)
The purpose of the present invention is to provide a technique for maintaining a maximum unipolar current density while improving I2t tolerance. This semiconductor device has a first doped layer (107) that is formed with a well layer (103) sandwiched between the first doped layer (107) and a Schottky interface (115). The first doped layer is formed from a surface layer of the well layer that is closer to the Schottky interface than a source layer (105) to below the source layer. Furthermore, the lower surface of the first doped layer is positioned below the Schottky interface.
(FR)
Le but de la présente invention est de fournir une technique permettant de maintenir une densité de courant unipolaire maximale tout en améliorant la tolérance l2t. Ce dispositif à semi-conducteur comporte une première couche dopée (107) qui est formée avec une couche de puits (103) prise en sandwich entre la première couche dopée (107) et une interface Schottky (115). La première couche dopée est formée à partir d'une couche de surface de la couche de puits qui est plus proche de l'interface Schottky qu'une couche de source (105) au-dessous de la couche de source. En outre, la surface inférieure de la première couche dopée est positionnée au-dessous de l'interface Schottky.
(JA)
I2t耐量を向上させつつ、最大ユニポーラ電流密度を維持するための技術を提供することを目的とする。半導体装置では、第1の不純物層(107)は、ショットキー界面(115)との間にウェル層(103)を挟んで形成される。また、第1の不純物層は、ソース層(105)よりもショットキー界面に近いウェル層の表層から、ソース層の下方にまで形成される。また、第1の不純物層の下面は、ショットキー界面よりも下方に位置する。
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