Processing

Please wait...

Settings

Settings

Goto Application

1. WO2020110170 - SEMICONDUCTOR PACKAGE AND PRODUCTION METHOD THEREFOR, AND SEMICONDUCTOR DEVICE

Publication Number WO/2020/110170
Publication Date 04.06.2020
International Application No. PCT/JP2018/043391
International Filing Date 26.11.2018
IPC
H01L 25/07 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04the devices not having separate containers
07the devices being of a type provided for in group H01L29/78
H01L 25/18 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
CPC
H01L 25/07
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; ; Multistep manufacturing processes thereof
03all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
04the devices not having separate containers
07the devices being of a type provided for in group H01L29/00
H01L 25/18
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; ; Multistep manufacturing processes thereof
18the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L51/00
Applicants
  • 三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP]/[JP]
Inventors
  • 中田 洋輔 NAKATA Yosuke
  • 藤田 淳 FUJITA Jun
Agents
  • 吉竹 英俊 YOSHITAKE Hidetoshi
  • 有田 貴弘 ARITA Takahiro
Priority Data
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR PACKAGE AND PRODUCTION METHOD THEREFOR, AND SEMICONDUCTOR DEVICE
(FR) BOÎTIER DE SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION, ET DISPOSITIF À SEMI-CONDUCTEURS
(JA) 半導体パッケージ、その製造方法、及び、半導体装置
Abstract
(EN)
The purpose of the present invention is to provide a technology with which it is possible to reduce cost and size of a semiconductor package. According to the present invention, a wiring element comprises: a second substrate; a plurality of first relay pads which are arranged on a surface opposite to a conductor substrate of the second substrate and which are connected to control pads of a plurality of semiconductor elements via wires; a plurality of second relay pads which are arranged on the surface opposite to the conductor substrate of the second substrate and which are provided in a number equal to or less than that of the first relay pads; and a plurality of wirings which are arranged on the surface opposite to the conductor substrate of the second substrate and which are configured to selectively connect between the first relay pads and the second relay pads.
(FR)
Le but de la présente invention est de fournir une technologie au moyen de laquelle il est possible de réduire la taille et le coût d'un boîtier de semi-conducteur. Selon la présente invention, un élément de câblage comprend : un second substrat ; une pluralité de premiers plots de relais qui sont agencés sur une surface en regard d'un substrat conducteur du second substrat et qui sont connectés à des plots de commande d'une pluralité d'éléments semi-conducteurs par l'intermédiaire de fils ; une pluralité de seconds plots de relais qui sont agencés sur la surface en regard du substrat conducteur du second substrat et qui sont disposés selon un nombre égal ou inférieur à celui des premiers plots de relais ; et une pluralité de câblages qui sont agencés sur la surface en regard du substrat conducteur du second substrat et qui sont configurés pour se connecter sélectivement entre les premiers plots de relais et les seconds plots de relais.
(JA)
半導体パッケージのコスト低減または小型化が可能な技術を提供することを目的とする。配線用素子は、第2基板と、第2基板の導体基板と逆側の面に配設され、複数の半導体素子の制御パッドとワイヤによって接続された複数の第1中継パッドと、第2基板の導体基板と逆側の面に配設され、個数が複数の第1中継パッドの個数以下である複数の第2中継パッドと、第2基板の導体基板と逆側の面に配設され、複数の第1中継パッドと複数の第2中継パッドとを選択的に接続する複数の配線とを含む。
Latest bibliographic data on file with the International Bureau