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1. WO2020109754 - METHOD, SYSTEM AND DEVICE FOR MAGNETIC MEMORY

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[ EN ]

CLAIMS

1. A bit-cell circuit, comprising: one or more non-volatile magnetic memory devices individually comprising:

a first magnetic tunnel junction component including a first terminal, the first magnetic tunnel junction component abutting a first surface of a metal layer; and

a second magnetic tunnel junction component including a second terminal, the second magnetic tunnel junction component abutting a second surface of the metal layer, wherein the metal layer includes a third terminal;

wherein the first magnetic tunnel junction component to store a first signal and/or state responsive to a voltage applied between the third terminal and the first terminal, and wherein the second magnetic tunnel junction component to store a second signal and/or state responsive to a voltage applied between the third terminal and the second terminal.

2. The bit-cell circuit of claim 1 , wherein the voltage applied between the third terminal and the first terminal and the voltage applied between the third terminal and the second terminal are applied concurrently.

3. The bit-cell circuit of claim 2, wherein the first magnetic tunnel junction component comprises one or more free magnetic layers and one or more pinned magnetic layers, wherein at least one of the one or more free magnetic layers are positioned substantially adjacent to the first surface of the metal layer.

4. The bit-cell circuit of claim 3, wherein the second magnetic tunnel junction component comprises one or more free magnetic layers and one or more pinned magnetic layers, wherein at least one of the one or more free magnetic layers are positioned substantially adjacent to the second surface of the metal layer.

5. The bit-cell circuit of claim 4, wherein the metal layer comprises a spin-orbit-torque (SOT) metal layer.

6. The bit-cell circuit of claim 5, further comprising a circuit to apply the voltage between the third terminal and the first terminal at least in part by applying a first signal to a first bit line to selectively conduct the first signal between the first bit-line and the first terminal at least in part responsive to an assertion of a bit-cell select signal, and the circuit further to apply the voltage between the third terminal and the second terminal at least in part by applying a second signal to a second bit-line to selectively conduct the second signal

between the second bit-line and the second terminal at least in part to implement an operation to write a first complementary pair of signals and/or states to the first and second magnetic tunnel junction components.

7. The bit-cell circuit of claim 6, further comprising a circuit to apply a logically high voltage level to the third terminal and to apply logically low voltage levels to the first and second bit-lines to implement the operation to write the first complementary pair of signals and/or states to the first and second magnetic tunnel junction components, wherein the first complementary pair of signals and/or states represents a value of“0” stored in the first magnetic tunnel component and a value of“1” stored in the second magnetic tunnel component.

8. The bit-cell circuit of claim 7, further comprising a circuit to apply a logically low voltage level to the third terminal and to apply logically high voltage levels to the first and second bit-lines to implement an operation to write a second complementary pair of signals and/or state6 to the first and second magnetic tunnel junction components, wherein the second complementary pair of signals and/or states represents a value of“1” stored in the first magnetic tunnel component and a value of“0” stored in the second magnetic tunnel component.

9. The bit-cell circuit of any of claims 5 to 8, wherein the first magnetic tunnel junction component to change magnetization vector orientation at a current greater in magnitude than the second magnetic tunnel junction component.

10. The bit-cell circuit of claim 9, further comprising:

a circuit to apply the voltage between the third terminal and the first terminal at least in part by applying a first signal to a first bit-line to selectively conduct the first signal between the first bit-line and the first terminal at least in part responsive to an assertion of a bit-cell select signal, and the circuit further to apply the voltage between the third terminal and the second terminal at least in part by applying a second signal to a second bit-line to selectively conduct the second signal between the second bit-line and the second terminal at least in part to implement an operation to write a first complementary pair of signals and/or states representative of values“1” and“0” to the first and second magnetic tunnel junction components, respectively; and

a circuit to apply a subsequent voltage across the third terminal and the second terminal to write a signal and/or state representative of the value of“1” in the second

magnetic tunnel junction component while maintaining the signal and/or state representative of the value of“1” in the first magnetic tunnel junction component.

11. The bit-cell circuit of any preceding claim, further comprising a circuit to sense a voltage level on a read bit-line selectively and/or variably electrically coupled to the metal layer to implement an operation to read the first and second signals and/or states stored in the first and second magnetic tunnel junction components.

12. The bit-cell circuit of claim 6, further comprising a circuit to precharge the first and second bit-lines to logically high voltage levels and to apply a logically low voltage level to the third terminal, wherein the circuit further to selectively couple the first bit-line to the first terminal and to selectively couple the second bit-line to the second terminal responsive to a subsequent assertion of the bit-cell select signal, and wherein the circuit further to sense a rate of discharge at the first and second bit-lines to implement an operation to read the first complementary pair of signals and/or states stored at the first and second magnetic tunnel junction components.

13. A method, comprising:

storing, at a first magnetic tunnel junction component abutting a first surface of a metal layer, a signal and/or state representative of a first value at least in part by applying a first voltage between a first terminal of the metal layer and a second terminal of the first magnetic tunnel junction; and

storing, at a second magnetic tunnel junction component abutting a second surface of the metal layer, a signal and/or state representative of a second value at least in part by applying a second voltage between the first terminal and a third terminal of the second magnetic tunnel junction.

14. The method of claim 13, wherein the applying the first voltage and applying the second voltage occur substantially concurrently.

15. The method of claim 14, wherein the first magnetic tunnel junction component comprises one or more free magnetic layers and one or more pinned magnetic layers, wherein at least one of the one or more free magnetic layers are positioned substantially adjacent to the first surface of the metal layer.

16. The method of claim 15, wherein the second magnetic tunnel junction component comprises one or more free magnetic layers and one or more pinned magnetic layers,

wherein at least one of the one or more free magnetic layers are positioned substantially adjacent to the second surface of the metal layer.

17. The method of claim of claim 16, wherein the metal layer comprises a spin-orbit-torque (SOT) metal layer.

18. The method of claim 17, further comprising applying the first voltage between the first terminal and the second terminal at least in part by applying a first signal to a first bit-line to selectively conduct the first signal between the first bit-line and the second terminal at least in part responsive to an assertion of a bit-cell select signal, and the applying the second voltage between the first terminal and the third terminal at least in part by applying a second signal to a second bit-line to selectively conduct the second signal between the second bit-line and the third terminal at least in part to implement an operation to write a first complementary pair of signals and/or states to the first and second magnetic tunnel junction components.

19. The method of claim 18, further comprising applying a logically high voltage level to the first terminal and applying logically low voltage levels to the first and second bit-lines to implement the operation to write the first complementary pair of signals and/or states to the first and second magnetic tunnel junction components, wherein the first complementary pair of signals and/or states represent a value of“0” stored in the first magnetic tunnel component and a value of“1” stored in the second magnetic tunnel component.

20. The method of claim 19, further comprising applying a logically low voltage level to the first terminal and applying logically high voltage levels to the first and second bit-lines to implement an operation to write a second complementary pair of signals and/or states to the first and second magnetic tunnel junction components, wherein the second

complementary pair of signals and/or states represents the value of“1” stored in the first magnetic tunnel component and the value of“0” stored in the second magnetic tunnel component.

21. The method of any of claims 17 to 20, wherein the first magnetic tunnel junction component to switch magnetization vector orientation in response to a current higher in magnitude than the second magnetic tunnel junction component.

22. The method of claim 21 , further comprising:

applying the voltage between the third terminal and the first terminal at least in part by applying a first signal to a first bit-line to selectively conduct the first signal between the first bit-line and the first terminal at least in part responsive to an assertion of a bit-cell select signal and applying the voltage between the third terminal and the second terminal at least in part by applying a second signal to a second bit-line to selectively conduct the second signal between the second bit-line and the second terminal at least in part to implement an operation to write a first complementary pair of signals and/or states representative of values“1” and“0” to the first and second magnetic tunnel junction components, respectively; and

applying a subsequent voltage across the first terminal and the third terminal to write a signal and/or state representative of a value of“1” in the second magnetic tunnel junction component while maintaining the signal and/or state representative of a value of “1” in the first magnetic tunnel junction component.

23. The method of any of claims 13 to 22, further comprising sensing a voltage level on a read bit-line selectively and/or variably electrically coupled to the metal layer to implement an operation to read the signals and/or states representative of the first and second values stored in the first and second magnetic tunnel junction components.

24. The method of claim 18, further comprising:

pre-charging the first and second bit-lines to logically high voltage levels and applying a logically low voltage level to the first terminal;

selectively electrically coupling the first bit-line to the second terminal;

selectively electrically coupling the second bit-line to the third terminal responsive to a subsequent assertion of the bit-cell select signal; and

sensing a rate of discharge at the first and second bit-lines to implement an operation to read the first complementary pair of values stored at the first and second magnetic tunnel junction components.