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1. WO2020109749 - APPARATUS AND DATA PROCESSING METHOD FOR TRANSACTIONAL MEMORY

Publication Number WO/2020/109749
Publication Date 04.06.2020
International Application No. PCT/GB2019/052967
International Filing Date 17.10.2019
IPC
G06F 9/30 2018.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/46 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
G06F 9/52 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
52Program synchronisation; Mutual exclusion, e.g. by means of semaphores
CPC
G06F 12/0842
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0806Multiuser, multiprocessor or multiprocessing cache systems
0842for multiprocessing or multitasking
G06F 2212/62
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
62Details of cache specific to multiprocessor cache arrangements
G06F 9/3004
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
3004to perform operations on memory
G06F 9/30087
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
30076to perform miscellaneous control operations, e.g. NOP
30087Synchronisation or serialisation instructions
G06F 9/467
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
466Transaction processing
467Transactional memory
G06F 9/5016
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
50Allocation of resources, e.g. of the central processing unit [CPU]
5005to service a request
5011the resources being hardware resources other than CPUs, Servers and Terminals
5016the resource being the memory
Applicants
  • ARM LIMITED [GB]/[GB]
Inventors
  • HORSNELL, Matthew James
  • GRISENTHWAITE, Richard Roy
Agents
  • BERRYMAN, Robert
Priority Data
1819348.228.11.2018GB
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) APPARATUS AND DATA PROCESSING METHOD FOR TRANSACTIONAL MEMORY
(FR) APPAREIL ET PROCÉDÉ DE TRAITEMENT DE DONNÉES POUR MÉMOIRE TRANSACTIONNELLE
Abstract
(EN)
In an apparatus (2) with transactional memory support circuitry (20), for a first type of transaction started using a first type of transaction start instruction, commitment of results of instructions executed speculatively following the first type of transaction start instruction are prevented until a transaction end instruction is reached. An abort is triggered when a conflict is detected between an address of a memory access from another thread and the addresses tracked for the transaction. For a second type of transaction started using a second type of transaction start instruction, an address of the read operation is marked as trackable whilst an address of a write operation is omitted from being marked as trackable. This allows an apparatus that supports transactional memory to also be used for multi-word address watching.
(FR)
La présente invention concerne un appareil (2) avec des circuits de support de mémoire transactionnelle (20), pour un premier type de transaction commencée en utilisant un premier type d'instruction de commencement de transaction, l'engagement en ce qui concerne des résultats d'instructions exécutées de manière spéculative après le premier type d'instruction de commencement de transaction est empêché jusqu'à ce qu'une instruction de fin de transaction soit atteinte. Un abandon est déclenché lorsqu'un conflit est détecté entre une adresse d'un accès de mémoire en provenance d'un autre fil et les adresses suivies pour la transaction. Pour un second type de transaction commencée en utilisant un second type d'instruction de commencement de transaction, une adresse de l'opération de lecture est marquée comme pouvant être suivie alors qu'une adresse d'une opération d'écriture n'est pas marquée comme pouvant être suivie. Ceci permet à un appareil qui supporte une mémoire transactionnelle d'être également utilisée pour une visualisation d'adresse multi-mot.
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