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1. WO2020109647 - COVERAGE BASED MICROELECTRONIC CIRCUIT, AND METHOD FOR PROVIDING A DESIGN OF A MICROELECTRONIC CIRCUIT

Publication Number WO/2020/109647
Publication Date 04.06.2020
International Application No. PCT/FI2018/050857
International Filing Date 27.11.2018
IPC
G06F 17/50 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
17Digital computing or data processing equipment or methods, specially adapted for specific functions
50Computer-aided design
G06F 11/07 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
H03K 19/007 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
007Fail-safe circuits
H03K 19/003 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
003Modifications for increasing the reliability
H03K 3/037 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
3Circuits for generating electric pulses; Monostable, bistable or multistable circuits
02Generators characterised by the type of circuit or by the means used for producing pulses
027by the use of logic circuits, with internal or external positive feedback
037Bistable circuits
G06F 1/3296 2019.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
26Power supply means, e.g. regulation thereof
32Means for saving power
3203Power management, i.e. event-based initiation of a power-saving mode
3234Power saving characterised by the action undertaken
3296by lowering the supply or operating voltage
CPC
G01R 31/3181
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
317Testing of digital circuits
3181Functional testing
G06F 1/3296
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
26Power supply means, e.g. regulation thereof
32Means for saving power
3203Power management, i.e. event-based initiation of power-saving mode
3234Power saving characterised by the action undertaken
3296by lowering the supply or operating voltage
G06F 11/07
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
H03K 19/00
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
H03K 19/003
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
003Modifications for increasing the reliability ; for protection
H03K 19/007
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
007Fail-safe circuits
Applicants
  • MINIMA PROCESSOR OY [FI]/[FI]
Inventors
  • GUPTA, Navneet
Agents
  • PAPULA OY
Priority Data
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) COVERAGE BASED MICROELECTRONIC CIRCUIT, AND METHOD FOR PROVIDING A DESIGN OF A MICROELECTRONIC CIRCUIT
(FR) CIRCUIT MICROÉLECTRONIQUE BASÉ SUR LA COUVERTURE, ET PROCÉDÉ PERMETTANT DE FOURNIR UNE CONCEPTION D'UN CIRCUIT MICROÉLECTRONIQUE
Abstract
(EN)
Microelectronic circuit com- prisesaplurality of logic units and register circuits, arranged into a plu- rality of processing paths, and a plu- rality of monitoring units associated with respective ones of said processing paths. Each of said monitoring units is configured to produce an observation signal as a response to anomalous opera- tion of the respective processing path. Each of said plurality of logic units belongs to one of a plurality of delay classes according to an amount of delay that it is likely to generate. Said de- lay classes comprise first, second, and third classes, of which the first class covers logic units that are likely to generate longest delays, the second class covers logic units that are likely to generate shorter delays than said first class, and the third class covers logic units that are likely to generate shorter delays than said second class. At least some of said plurality of pro- cessing paths comprise logic units be- longing to said second class but are without monitoring units. At least some of said plurality of processing paths comprise logic units belonging to said third class but have monitoring units associated with them.
(FR)
L'invention concerne un circuit microélectronique comprenant plusieurs unités logiques et circuits de registre, agencés en plusieurs trajets de traitement, et plusieurs unités de surveillance associées à des trajets de traitement respectifs parmi lesdits trajets de traitement. Chacune desdites unités de surveillance est configurée pour produire un signal d'observation en réponse à un fonctionnement anormal du trajet de traitement respectif. Chacune desdites multiples unités logiques appartient à une classe de retard parmi plusieurs classes de retard selon une quantité de retard qu'il est susceptible de générer. Lesdites classes de retard comprennent des première, deuxième et troisième classes, la première classe couvrant des unités logiques qui sont susceptibles de générer des retards plus longs, la deuxième classe couvrant des unités logiques qui sont susceptibles de générer des retards plus courts que ladite première classe, et la troisième classe couvrant des unités logiques qui sont susceptibles de générer des retards plus courts que ladite deuxième classe. Au moins certains desdits multiples trajets de traitement comprennent des unités logiques appartenant à ladite deuxième classe mais n'ont pas d'unités de surveillance. Au moins certains desdits multiples trajets de traitement comprennent des unités logiques appartenant à ladite troisième classe mais ont des unités de surveillance leur étant associées.
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