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1. WO2020107754 - EPITAXIAL LAYER STRUCTURE FOR INCREASING THRESHOLD VOLTAGE OF GAN-ENHANCED MOSFET AND DEVICE FABRICATION METHOD

Publication Number WO/2020/107754
Publication Date 04.06.2020
International Application No. PCT/CN2019/079417
International Filing Date 25.03.2019
IPC
H01L 29/778 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
778with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 21/335 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334Multistep processes for the manufacture of devices of the unipolar type
335Field-effect transistors
CPC
H01L 29/06
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
H01L 29/205
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
12characterised by the materials of which they are formed
20including, apart from doping materials or other impurities, only AIIIBV compounds
201including two or more compounds ; , e.g. alloys
205in different semiconductor regions ; , e.g. heterojunctions
H01L 29/423
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
41characterised by their shape, relative sizes or dispositions
423not carrying the current to be rectified, amplified or switched
H01L 29/778
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
76Unipolar devices ; , e.g. field effect transistors
772Field effect transistors
778with two-dimensional charge carrier gas channel, e.g. HEMT ; ; with two-dimensional charge-carrier layer formed at a heterojunction interface
H01L 29/78
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
76Unipolar devices ; , e.g. field effect transistors
772Field effect transistors
78with field effect produced by an insulated gate
Applicants
  • 北京大学 PEKING UNIVERSITY [CN]/[CN]
Inventors
  • 王茂俊 WANG, Maojun
  • 陶明 TAO, Ming
Agents
  • 北京万象新悦知识产权代理有限公司 BEIJING WANXIANGXINYUE INTELLECTUAL PROPERTY OFFICE
Priority Data
201811422595.427.11.2018CN
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) EPITAXIAL LAYER STRUCTURE FOR INCREASING THRESHOLD VOLTAGE OF GAN-ENHANCED MOSFET AND DEVICE FABRICATION METHOD
(FR) STRUCTURE DE COUCHE ÉPITAXIALE POUR AUGMENTER LA TENSION SEUIL D'UN MOSFET AMÉLIORÉ PAR GAN ET PROCÉDÉ DE FABRICATION DE DISPOSITIF
(ZH) 一种提高GaN增强型MOSFET阈值电压的外延层结构及器件制备
Abstract
(EN)
An epitaxial layer structure for increasing a threshold voltage of a GaN-enhanced MOSFET and a device fabrication method employing the structure, relating to the field of power electronic devices and power switches. A substrate, a GaN buffer layer, an intrinsic GaN layer, an Mg-doped P-type GaN layer, a GaN channel layer, and an AlGaN barrier layer are sequentially provided, from bottom to top, in the epitaxial layer structure. A passivation layer, a recessed gate, planar isolation, an insulated gate medium layer, an ohmic contact, a gate ohmic metal electrode, and a source-drain ohmic metal electrode are formed on the structure by means of a recessed gate process, so as to fabricate a GaN-enhanced MOSFET having a high threshold voltage. In the present invention, the P-type GaN layer is inserted into the intrinsic GaN layer, and after etching has been completely performed thereon, a channel inversion region has the P-type GaN layer in addition to the intrinsic GaN layer, thereby greatly increasing a threshold voltage of a device. The invention facilitates an improvement in the reliability of a GaN-enhanced device in practical applications, and widens an application range of the device in the field of power switches.
(FR)
Structure de couche épitaxiale pour augmenter une tension seuil d'un MOSFET amélioré par GaN et procédé de fabrication de dispositif employant la structure, concernant le domaine de dispositifs électroniques de puissance et des commutateurs de puissance. Un substrat, une couche tampon de GaN, une couche de GaN intrinsèque, une couche de GaN de type P dopée au Mg, une couche de canal de GaN et une couche barrière d'AlGaN sont séquentiellement disposés, de bas en haut, dans la structure de couche épitaxiale. Une couche de passivation, une grille évidée, une isolation plane, une couche de milieu de grille isolée, un contact ohmique, une électrode métallique ohmique de grille, et une électrode métallique ohmique de source-drain sont formées sur la structure au moyen d'un processus de grille évidée, de façon à fabriquer un MOSFET amélioré par GaN ayant une tension seuil élevée. Selon la présente invention, la couche de GaN de type P est introduite dans la couche de GaN intrinsèque, et après qu'une gravure a été complètement effectuée sur celle-ci, une région d'inversion de canal comporte la couche de GaN de type P en plus de la couche de GaN intrinsèque, ce qui permet d'augmenter considérablement une tension seuil d'un dispositif. L'invention facilite une amélioration de la fiabilité d'un dispositif amélioré par GaN dans des applications pratiques, et élargit une plage d'application du dispositif dans le domaine des commutateurs de puissance.
(ZH)
一种提高GaN增强型MOSFET阈值电压的外延层结构及基于该结构的器件制备方法,涉及电力电子器件及功率开关领域。该外延层结构自下而上依次为衬底、GaN缓冲层、本征GaN层、Mg掺杂P型GaN层、GaN沟道层和AlGaN势垒层。在该结构上用凹槽栅工艺形成钝化层、凹槽栅、平面隔离、绝缘栅介质层、欧姆接触以及栅和源漏欧姆金属电极即可制备出高阈值电压增强型GaN MOSFET。本发明在本征GaN层中插入P型GaN层,将其完全刻蚀后,沟道反型区域除了本征GaN层还有P型GaN层,由此可以极大提高器件的阈值电压。有利于解决GaN增强型器件在实际应用中的可靠性问题,扩宽了其在功率开关领域的应用。
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