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1. WO2020107671 - SEMICONDUCTOR ASSEMBLY AND METHOD FOR MANUFACTURING SAME

Publication Number WO/2020/107671
Publication Date 04.06.2020
International Application No. PCT/CN2019/071289
International Filing Date 11.01.2019
IPC
H01L 29/786 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
786Thin-film transistors
CPC
H01L 27/1248
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12the substrate being other than a semiconductor body, e.g. an insulating body
1214comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
1248with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
H01L 27/1259
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12the substrate being other than a semiconductor body, e.g. an insulating body
1214comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
1259Multistep manufacturing methods
Applicants
  • 武汉华星光电技术有限公司 WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN]/[CN]
Inventors
  • 肖东辉 XIAO, Donghui
Agents
  • 深圳翼盛智成知识产权事务所(普通合伙) ESSEN PATENT&TRADEMARK AGENCY
Priority Data
201811452431.630.11.2018CN
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) SEMICONDUCTOR ASSEMBLY AND METHOD FOR MANUFACTURING SAME
(FR) ENSEMBLE SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
(ZH) 半导体组件及其制造方法
Abstract
(EN)
A semiconductor assembly, comprising: a substrate (10); a polysilicon layer (50) formed on the substrate (10), the polysilicon layer comprising a source, a channel, and a drain, wherein the source and the drain are formed on either side of the polysilicon layer (50) and the channel is formed between the source and the drain; a gate insulating layer (60) formed on the polysilicon layer (50); a gate (70) formed on the gate insulating layer (60) directly above the channel; inner dielectric layers (80, 90) formed above the gate (70) and covering the gate (70), wherein the inner dielectric layers (80, 90) are formed into hydrogenated inner dielectric layers (80, 90) after being implanted with a hydrogen atom by means of an ion implant (100) and being subjected to high-temperature quick tempering; a metal wire passing through the upper surfaces of the hydrogenated inner dielectric layers (80, 90); and a passivation layer covering the hydrogenated inner dielectric layers (80, 90). Also disclosed is a method for manufacturing the semiconductor assembly.
(FR)
L'invention concerne un ensemble semi-conducteur, comprenant : un substrat (10) ; une couche de polysilicium (50) formée sur le substrat (10), la couche de polysilicium comprenant une source, un canal et un drain, la source et le drain étant formés de chaque côté de la couche de polysilicium (50) et le canal est formé entre la source et le drain ; une couche d'isolation de grille (60) formée sur la couche de polysilicium (50) ; une grille (70) formée sur la couche d'isolation de grille (60) directement au-dessus du canal ; des couches diélectriques internes (80, 90) formées au-dessus de la grille (70) et recouvrant la grille (70), les couches diélectriques internes (80, 90) étant formées en couches diélectriques internes hydrogénées (80, 90) après avoir été implantées avec un atome d'hydrogène au moyen d'un implant ionique (100) et étant soumises à une trempe rapide à haute température ; un fil métallique passant à travers les surfaces supérieures des couches diélectriques internes hydrogénées (80, 90) ; et une couche de passivation recouvrant les couches diélectriques internes hydrogénées (80, 90). La présente invention a également trait à un procédé de fabrication de l'ensemble semi-conducteur.
(ZH)
一种半导体组件,包括基板(10);形成在基板(10)上的多晶硅层(50),多晶硅层包括源极、通道及漏极,其中源极及漏极形成在多晶硅层(50)的二侧,形成在源极及漏极之间的通道;形成在多晶硅层(50)上的栅极绝缘层(60);形成在栅极绝缘层(60)上的栅极(70),且栅极(70)形成在通道的正上方;形成在栅极(70)上方且覆盖栅极(70)的内层介电层(80、90),内层介电层(80、90)通过离子布植(100)植入氢原子且经高温快速回火形成氢化的内层介电层(80、90);穿过氢化的内层介电层(80、90)的上表面的金属导线,且分别与源极及漏极接触;以及覆盖氢化的内层介电层(80、90)的钝化层。还公开一种上述半导体组件的制造方法。
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