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1. WO2020107447 - METHOD FOR MANUFACTURING CHIP AND CHIP STRUCTURE

Publication Number WO/2020/107447
Publication Date 04.06.2020
International Application No. PCT/CN2018/118696
International Filing Date 30.11.2018
IPC
H01L 21/98 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
98Assembly of devices consisting of solid state components formed in or on a common substrate; Assembly of integrated circuit devices
H01L 21/78 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
CPC
H01L 21/78
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
Applicants
  • 北京比特大陆科技有限公司 BITMAIN TECHNOLOGIES INC. [CN]/[CN]
Inventors
  • 王逵 WANG, Kui
Agents
  • 北京同立钧成知识产权代理有限公司 LEADER PATENT & TRADEMARK FIRM
Priority Data
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) METHOD FOR MANUFACTURING CHIP AND CHIP STRUCTURE
(FR) PROCÉDÉ DE FABRICATION DE PUCE ET STRUCTURE DE PUCE
(ZH) 芯片制造方法及芯片结构
Abstract
(EN)
Disclosed are a method for manufacturing a chip and a chip structure. The method comprises: fabricating multiple first mask units on a first wafer, each of the first mask units comprising one or more of a processor cluster, a first memory, a storage channel, a serial channel, a controller and a bus interface module; fabricating a first connecting point on the first wafer; fabricating multiple second mask units on a second wafer, each of the second mask units comprising one or more of a second memory, an extension module and a bus interconnection module; fabricating a second connecting point on the second wafer; and bonding the first wafer and the second wafer together through the first connecting point and the second connecting point, and dicing the wafers, with the chip size obtained by means of dicing being the same as the size of the second mask units. The technical solution of this disclosure can greatly save on the one-time expense generated during chip production, and can not only save on time and labor costs, but can also reduce the production risk and production cost of products of each single specification or performance.
(FR)
Procédé de fabrication d'une puce et structure de puce. Le procédé consiste à : fabriquer de multiples premières unités de masque sur une première plaquette, chacune des premières unités de masque comprenant un ou plusieurs éléments parmi un groupe de processeurs, une première mémoire, un canal de stockage, un canal série, un dispositif de commande et un module d'interface de bus ; fabriquer un premier point de connexion sur la première plaquette ; fabriquer de multiples secondes unités de masque sur une seconde plaquette, chacune des secondes unités de masque comprenant un ou plusieurs éléments parmi une seconde mémoire, un module d'extension et un module d'interconnexion de bus ; fabriquer un second point de connexion sur la seconde plaquette ; et relier la première plaquette et de la seconde plaquette l'une à l'autre par l'intermédiaire du premier point de connexion et du second point de connexion, et découper en dés les plaquettes, la taille de puce obtenue au moyen du découpage en dés étant la même que la taille des secondes unités de masque. La solution technique de la présente invention peut réduire considérablement les dépenses ponctuelles générées pendant la production de puce, et peut non seulement économiser du temps et des coûts de main-d'oeuvre, mais peut également réduire le risque de production et le coût de production de produits de chaque spécification ou performance individuelle.
(ZH)
本公开公开了一种芯片制造方法及芯片结构。所述方法包括:在第一晶圆上制作多个第一掩膜单元,第一掩膜单元包括处理器簇群、第一存储器、存储通道、串行通道、控制器和总线接口模块中的一种或多种;在第一晶圆上制作第一连接点;在第二晶圆上制作多个第二掩膜单元,第二掩膜单元包括第二存储器、扩展模块和总线互联模块中的一种或多种;在第二晶圆上制作第二连接点;将第一晶圆和第二晶圆通过第一连接点和第二连接点键合在一起,对晶圆进行切割,切割得到的芯片尺寸与第二掩膜单元的尺寸相同。本公开技术方案可以大大节省芯片生产时产生的一次性费用,不仅能够节省时间和人力成本,还能够降低每个单一规格或性能产品的生产风险和生产成本。
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