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1. WO2020097177 - SYSTEMS AND METHODS FOR STALLING HOST PROCESSOR

Publication Number WO/2020/097177
Publication Date 14.05.2020
International Application No. PCT/US2019/060028
International Filing Date 06.11.2019
IPC
G06F 21/12 2013.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
21Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
10Protecting distributed programs or content, e.g. vending or licensing of copyrighted material
12Protecting executable software
G06F 9/30 2018.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/48 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
48Program initiating; Program switching, e.g. by interrupt
G06F 13/16 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
G06F 13/24 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
20for access to input/output bus
24using interrupt
G06F 21/52 2013.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
21Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
50Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
52during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure
CPC
G06F 13/16
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
G06F 13/24
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
20for access to input/output bus
24using interrupt
G06F 21/121
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
21Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
10Protecting distributed programs or content, e.g. vending or licensing of copyrighted material
12Protecting executable software
121Restricting unauthorised execution of programs
G06F 21/52
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
21Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
50Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
52during program execution, e.g. stack integrity ; ; Preventing unwanted data erasure; Buffer overflow
G06F 21/554
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
21Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
50Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
55Detecting local intrusion or implementing counter-measures
554involving event detection and direct action
G06F 21/56
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
21Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
50Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
55Detecting local intrusion or implementing counter-measures
56Computer malware detection or handling, e.g. anti-virus arrangements
Applicants
  • DOVER MICROSYSTEMS, INC. [US]/[US]
Inventors
  • MILBURN, Steven
  • SULLIVAN, Gregory, T.
Agents
  • MORRIS, James, H.
  • AMUNDSEN, Eric, L.
  • ATTISHA, Michael, J.
  • ALAM, Saad
  • BAKER, C., Hunter
Priority Data
62/756,46506.11.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SYSTEMS AND METHODS FOR STALLING HOST PROCESSOR
(FR) SYSTÈMES ET PROCÉDÉS POUR SUSPENDRE LE FONCTIONNEMENT D'UN PROCESSEUR HÔTE
Abstract
(EN)
Systems and methods for stalling a host processor. In some embodiments, the host processor may be caused to initiate one or more selected transactions, wherein the one or more selected transactions comprise a data bus transaction. The host processor may be prevented from completing the data bus transaction, to thereby stall the host processor, wherein: the act of causing the host processor to initiate one or more selected transactions comprises asserting an interrupt to cause the host processor to load, from an interrupt vector address, one or more instructions of an interrupt handler corresponding to the interrupt; the one or more instructions, when executed by the host processor, cause the host processor to check for a cause of the interrupt; and the act of preventing the host processor from completing the data bus transaction comprises preventing the host processor from checking for a cause of the interrupt.
(FR)
Systèmes et procédés pour suspendre le fonctionnement d'un processeur hôte. Dans certains modes de réalisation, le processeur hôte peut être amené à initier une ou plusieurs transactions sélectionnées, les une ou plusieurs transactions sélectionnées comprenant une transaction de bus de données. Le processeur hôte peut être empêché de mener à bien la transaction de bus de données, pour ainsi suspendre le fonctionnement du processeur hôte. L'action consistant à amener le processeur hôte à initier une ou plusieurs transactions sélectionnées comprend l'assertion d'une interruption pour amener le processeur hôte à charger, d'une adresse de vecteur d'interruption, une ou plusieurs instructions d'un gestionnaire d'interruption correspondant à l'interruption ; les une ou plusieurs instructions, lorsqu'elles sont exécutées par le processeur hôte, amènent le processeur hôte à vérifier une cause de l'interruption ; et l'action d'empêcher le processeur hôte de mener à bien la transaction de bus de données consiste à empêcher le processeur hôte de vérifier une cause de l'interruption.
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