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1. WO2020096309 - INTERPOSER

Publication Number WO/2020/096309
Publication Date 14.05.2020
International Application No. PCT/KR2019/014842
International Filing Date 04.11.2019
IPC
H01L 23/00 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
H01L 23/552 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
552Protection against radiation, e.g. light
H01L 23/538 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
538the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/498 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488consisting of soldered or bonded constructions
498Leads on insulating substrates
CPC
H01L 2224/16225
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
161Disposition
16151the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
16221the body and the item being stacked
16225the item being non-metallic, e.g. insulating substrate with or without metallisation
Applicants
  • 주식회사 아모센스 AMOSENSE CO., LTD [KR]/[KR]
Inventors
  • 오창우 OH, Changwoo
  • 이길선 LEE, Gilseon
  • 신정균 SHIN, Jungkyun
  • 안영준 AN, Youngjun
Agents
  • 김철진 KIM, Churchill
Priority Data
10-2018-013685408.11.2018KR
10-2019-013668230.10.2019KR
Publication Language Korean (KO)
Filing Language Korean (KO)
Designated States
Title
(EN) INTERPOSER
(FR) INTERPOSEUR
(KO) 인터포저
Abstract
(EN)
The present invention relates to an interposer (300), wherein the interposer (300) comprises: a support (310) which is made of a ceramic material; a connecting electrode (320) for connecting the upper surface and the lower surface of the support (310); and a shielding material (330) which is disposed on the outer surface of the support, and at least a part of the interposer (300) is disposed along the edge of a substrate (100) and electrically connects the substrate (100) to a substrate (200). The present invention has advantages of being capable of being implemented with a fine pattern by applying a ceramic material, and contributing to high performance and miniaturization of electronic devices by increasing dimensional stability by preventing warping of the ceramic, thereby increasing the reliability of signal transmission.
(FR)
La présente invention concerne un interposeur (300), l'interposeur (300) comprenant : un support (310) qui est fait d'un matériau céramique ; une électrode de connexion (320) pour relier la surface supérieure et la surface inférieure du support (310) ; et un matériau de blindage (330) qui est disposé sur la surface externe du support, et au moins une partie de l'interposeur (300) est disposée le long du bord d'un substrat (100) et connecte électriquement le substrat (100) à un substrat (200). La présente invention présente les avantages d'être mise en œuvre avec un motif fin par l'application d'un matériau céramique, et de contribuer à une performance et une miniaturisation élevées de dispositifs électroniques par augmentation de la stabilité dimensionnelle en empêchant le gauchissement de la céramique, ce qui permet d'augmenter la fiabilité de transmission de signal.
(KO)
본 발명은 인터포저에 관한 것으로, 인터포저(300)는 세라믹 재질로 이루어진 지지체(310)와 지지체(310)의 상면과 하면을 연결하는 연결 전극(320)과 지지체의 외측면에 배치되는 차폐재(330)를 포함하며, 적어도 일부가 기판(100) 가장자리를 따라 배치되어 기판(100)과 기판(200)을 전기적으로 연결한다. 본 발명은 세라믹 재질을 적용하여 미세패턴 구현이 가능하고 세라믹의 휨을 방지하여 치수 안정성을 높이며 이를 통해 신호전송의 신뢰성을 높이므로 전자기기의 고성능 및 소형화 구현에 기여할 수 있는 이점이 있다.
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