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1. WO2020095540 - IMAGING DEVICE AND ELECTRONIC DEVICE

Publication Number WO/2020/095540
Publication Date 14.05.2020
International Application No. PCT/JP2019/036091
International Filing Date 13.09.2019
IPC
H04N 5/367 2011.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
NPICTORIAL COMMUNICATION, e.g. TELEVISION
5Details of television systems
30Transforming light or analogous information into electric information
335using solid-state image sensors
357Noise processing, e.g. detecting, correcting, reducing or removing noise
365applied to fixed-pattern noise, e.g. non-uniformity of response
367applied to defects, e.g. non-responsive pixels
G01R 31/02 2006.01
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
02Testing of electric apparatus, lines, or components for short-circuits, discontinuities, leakage, or incorrect line connection
H01L 21/3205 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H01L 21/768 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 27/146 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144Devices controlled by radiation
146Imager structures
Applicants
  • ソニーセミコンダクタソリューションズ株式会社 SONY SEMICONDUCTOR SOLUTIONS CORPORATION [JP]/[JP]
Inventors
  • 朝倉 ルォンフォン ASAKURA Luonghung
Agents
  • 山本 孝久 YAMAMOTO Takahisa
  • 吉井 正明 YOSHII Masaaki
Priority Data
2018-20946007.11.2018JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) IMAGING DEVICE AND ELECTRONIC DEVICE
(FR) DISPOSITIF D'IMAGERIE ET DISPOSITIF ÉLECTRONIQUE
(JA) 撮像装置及び電子機器
Abstract
(EN)
The present invention is obtained by stacking: a first substrate on which a pixel array portion obtained by arranging, in a matrix shape, pixels each including a light-receiving part, is formed; and a second substrate on which pixel control parts for controlling the pixels are formed. The first substrate is provided with: a first wire for transmitting a first voltage; a second wire for transmitting a second voltage; and a defect detection circuit that, when the pixel array portion is divided into a plurality of pixel blocks with a plurality of pixel columns or a plurality of pixel rows defined as units, detects a defect for each pixel block. When a wire defect is detected, the defect detection circuit, for each pixel block, connects in series a plurality of wires corresponding to the plurality of pixel columns or the plurality of pixel rows, connects, to the first wire, one end of a wire chain, of each pixel block, which is obtained by connecting the wires in series, connects the other end to the second wire, and detects the wire defect on the basis of an electric potential at an intermediate position of the wire chain.
(FR)
La présente invention est obtenue par empilement : d'un premier substrat sur lequel une partie de réseau de pixels obtenue par agencement, dans une forme de matrice, des pixels comprenant chacun une partie de réception de lumière, est formé; et un second substrat sur lequel des parties de commande de pixel pour commander les pixels sont formées. Le premier substrat est pourvu : d'un premier fil pour transmettre une première tension; d'un second fil pour transmettre une seconde tension; et d'un circuit de détection de défaillance qui, lorsque la partie de matrice de pixels est divisée en une pluralité de blocs de pixels avec une pluralité de colonnes de pixels ou une pluralité de rangées de pixels définies en tant qu'unités, détecte une défaillance pour chaque bloc de pixels. Lorsqu'une défaillance de fil est détectée, le circuit de détection de défaillance, pour chaque bloc de pixel, connecte en série une pluralité de fils correspondant à la pluralité de colonnes de pixels ou à la pluralité de rangées de pixels, connecte, au premier fil, une extrémité d'une chaîne de fils, de chaque bloc de pixel, qui est obtenu en connectant les fils en série, connecte l'autre extrémité au second fil, et détecte la défaillance de fil sur la base d'un potentiel électrique à une position intermédiaire de la chaîne de fil.
(JA)
受光部を含む画素が行列状に配置されて成る画素アレイ部が形成された第1の基板、及び、画素を制御する画素制御部が形成された第2の基板が積層されて成る。第1の基板は、第1の電圧を伝送する第1の配線、第2の電圧を伝送する第2の配線、及び、画素アレイ部を、複数の画素列又は複数の画素行を単位として複数の画素ブロックに分割したとき、画素ブロック毎に、配線不良の検出を行う不良検出回路を備える。不良検出回路は、配線不良の検出時に、画素ブロック毎に、複数の画素列又は複数の画素行に対応する複数の配線を直列に接続し、各画素ブロックの直列に接続された配線チェーンの一端を第1の配線に接続し、他端を第2の配線に接続し、配線チェーンの中間位置の電位に基づいて配線不良の検出を行う。
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