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1. WO2020095148 - SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS

Publication Number WO/2020/095148
Publication Date 14.05.2020
International Application No. PCT/IB2019/059245
International Filing Date 29.10.2019
IPC
G11C 5/02 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by group G11C11/63
02Disposition of storage elements, e.g. in the form of a matrix array
H01L 21/8242 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology
8239Memory structures
8242Dynamic random access memory structures (DRAM)
H01L 27/108 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
H01L 29/786 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
786Thin-film transistors
G11C 29/00 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
Applicants
  • 株式会社半導体エネルギー研究所 SEMICONDUCTOR ENERGY LABORATORY CO., LTD. [JP]/[JP]
Inventors
  • 大貫達也 ONUKI, Tatsuya
  • 松嵜隆徳 MATSUZAKI, Takanori
  • 熱海知昭 ATSUMI, Tomoaki
  • 山崎舜平 YAMAZAKI, Shunpei
Priority Data
2018-21069508.11.2018JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET APPAREIL ÉLECTRONIQUE
(JA) 半導体装置、及び電子機器
Abstract
(EN)
Provided is a semiconductor device in which data is written to a separate memory cell instead of a defective memory cell. The semiconductor device comprises a first circuit and a second circuit located on the first circuit. The first circuit corresponds to a storage unit and includes a memory cell and a redundant memory cell. The second circuit corresponds to a control unit and includes a third circuit and a fourth circuit. The memory cell is electrically connected to the third circuit, the redundant memory cell is electrically connected to the third circuit, and the third circuit is electrically connected to the fourth circuit. The fourth circuit has the function of transmitting, to the third circuit, data to be written to the memory cell or the redundant memory cell. The third circuit has the function, if the memory cell is a defective cell, of placing the memory cell and the fourth circuit in a non-conducting state, placing the redundant memory cell and the fourth circuit in a conductive state, and transmitting the data to the redundant memory cell.
(FR)
L'invention concerne un dispositif à semi-conducteur dans lequel des données sont écrites dans une cellule de mémoire séparée au lieu d'une cellule de mémoire défectueuse. Le dispositif à semi-conducteur comprend un premier circuit et un second circuit situé sur le premier circuit. Le premier circuit correspond à une unité de stockage et comprend une cellule de mémoire et une cellule de mémoire redondante. Le second circuit correspond à une unité de commande et comprend un troisième circuit et un quatrième circuit. La cellule de mémoire est connectée électriquement au troisième circuit, la cellule de mémoire redondante est électriquement connectée au troisième circuit, et le troisième circuit est électriquement connecté au quatrième circuit. Le quatrième circuit a pour fonction de transmettre au troisième circuit des données à écrire dans la cellule de mémoire ou dans la cellule de mémoire redondante. Le troisième circuit a pour fonction, si la cellule de mémoire est une cellule défectueuse, de placer la cellule de mémoire et le quatrième circuit dans un état non conducteur, placer la cellule de mémoire redondante et le quatrième circuit dans un état conducteur, et transmettre les données à la cellule de mémoire redondante.
(JA)
要約書 不良のメモリセルの代わりに、別のメモリセルにデータを書き込む半導体装置を提供する。 第1回路と、第1回路上に位置する第2回路と、有する半導体装置であって、第1回路は、記憶部 に相当し、メモリセルと、冗長メモリセルと、を有し、第2回路は、制御部に相当し、第3回路と、 第4回路と、を有する。メモリセルは、第3回路に電気的に接続され、冗長メモリセルは、第3回 路に電気的に接続され、第3回路は、第4回路に電気的に接続されている。第4回路は、メモリセ ル又は冗長メモリセルに書き込むためのデータを第3回路に送信する機能を有し、第3回路は、メ モリセルが不良セルであった場合に、メモリセルと第4回路とを非導通状態にし、冗長メモリセル と前記第4回路と導通状態にして、当該データを冗長メモリセルに送信する機能を有する。
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